From patchwork Tue Apr 12 14:32:38 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michael Walle X-Patchwork-Id: 12810866 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id DF3E5C433EF for ; Tue, 12 Apr 2022 14:37:20 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=ZkUwVY7o77jRWL6Yw9WudthD45yv8vwgPW4ffmRMxWU=; b=DmgV/zswDLi8wF xsIGKjbo4thnbnIsvsNvxkGNj4P+gwkIucs6U/TdaLspwevZMcEJdjZOmdyJtf6ooynP9vWQNJmRc F5KARa9SF3Dj+NoQqRCxVzM/UA+33c2HJVVNcYasOelESbDkTWacTgBxfgMNCoRGKTysWpgQ67SHd GngwhE7OB8PF07SOMgmV71LhhFgYnNM8TrqeEeTT20RyBaosf9K9udK8gIUfjopXToUDhfPNHvNfm wjGzR2ZgGV5tKFbRPDX4rQ3gPqHM873DGdFt5FR2fycAi3Y1STZYnB8M+Ig9uF3cOsXEpO1dhq9K6 y6zYsyOYnrHx/McVxQMA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1neHcq-00EnmI-P9; Tue, 12 Apr 2022 14:36:12 +0000 Received: from ssl.serverraum.org ([2a01:4f8:151:8464::1:2]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1neHcW-00Enf1-IR for linux-arm-kernel@lists.infradead.org; Tue, 12 Apr 2022 14:35:54 +0000 Received: from mwalle01.kontron.local. (unknown [213.135.10.150]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange ECDHE (P-384) server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by ssl.serverraum.org (Postfix) with ESMTPSA id 32CF222249; Tue, 12 Apr 2022 16:35:48 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=walle.cc; s=mail2016061301; t=1649774148; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=G/hnT3AEhxVxbNwEdDE7vvgvmJxgXYZA0Ny8VTY14TA=; b=Ww/nu+x4QXsYJMEE0AH07YIcmC0qeLlkPD42SFTL3CJUgKcpbHUiQa9cSpRkeoL0j/XBnB CyZG6NFX/0k9k9+JMFI3cJY8Dn4XEHaS9poZLGPVrKpvaiCyQYfCRhNGV1zFje/qNFHRq6 LZqy5hFLZVnhPBycjABPOchfUfssPnU= From: Michael Walle To: Shawn Guo , Sascha Hauer Cc: Rob Herring , Krzysztof Kozlowski , Pengutronix Kernel Team , Fabio Estevam , NXP Linux Team , Heiko Thiery , Li Yang , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Michael Walle Subject: [PATCH v3 2/2] arm64: dts: imx8mn: add 8MNANOD3L-EVK device tree Date: Tue, 12 Apr 2022 16:32:38 +0200 Message-Id: <20220412143238.1925059-3-michael@walle.cc> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20220412143238.1925059-1-michael@walle.cc> References: <20220412143238.1925059-1-michael@walle.cc> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220412_073552_967460_0A70A241 X-CRM114-Status: GOOD ( 14.16 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Add a device tree for the 8MNANOD3L-EVK eval board which features an IMX8MN SoC. It is similar to the 8MNANODLPD4-EVK eval board except it has an IMX8MN UltraLite SoC and DDR3L memory. It esp. differs in the PMIC configuration because the SoC has a smaller package and thus the ARM core voltage is combined with the SoC voltage and the DDR voltage is 1.35V for the DDR3L memory. Signed-off-by: Michael Walle --- changes since v2: - new patch arch/arm64/boot/dts/freescale/Makefile | 1 + .../boot/dts/freescale/imx8mn-ddr3l-evk.dts | 114 ++++++++++++++++++ 2 files changed, 115 insertions(+) create mode 100644 arch/arm64/boot/dts/freescale/imx8mn-ddr3l-evk.dts diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile index 85c2c9ba5110..bdb76e67ccfe 100644 --- a/arch/arm64/boot/dts/freescale/Makefile +++ b/arch/arm64/boot/dts/freescale/Makefile @@ -73,6 +73,7 @@ dtb-$(CONFIG_ARCH_MXC) += imx8mn-beacon-kit.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mn-bsh-smm-s2.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mn-bsh-smm-s2pro.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mn-evk.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8mn-ddr3l-evk.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mn-ddr4-evk.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mn-tqma8mqnl-mba8mx.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mn-var-som-symphony.dtb diff --git a/arch/arm64/boot/dts/freescale/imx8mn-ddr3l-evk.dts b/arch/arm64/boot/dts/freescale/imx8mn-ddr3l-evk.dts new file mode 100644 index 000000000000..000e2c0596df --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mn-ddr3l-evk.dts @@ -0,0 +1,114 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +/dts-v1/; + +#include "imx8mn.dtsi" +#include "imx8mn-evk.dtsi" +#include + +/ { + model = "NXP i.MX8MNano DDR3L EVK board"; + compatible = "fsl,imx8mn-ddr3l-evk", "fsl,imx8mn"; +}; + +&A53_0 { + cpu-supply = <&buck1>; +}; + +&A53_1 { + cpu-supply = <&buck1>; +}; + +&A53_2 { + cpu-supply = <&buck1>; +}; + +&A53_3 { + cpu-supply = <&buck1>; +}; + +&i2c1 { + pmic: pmic@25 { + compatible = "nxp,pca9450b"; + reg = <0x25>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pmic>; + interrupt-parent = <&gpio1>; + interrupts = <3 IRQ_TYPE_LEVEL_LOW>; + + regulators { + buck1: BUCK1 { + regulator-name = "VDD_SOC_0V9"; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <950000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <3125>; + }; + + buck4: BUCK4 { + regulator-name = "VDD_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + buck5: BUCK5 { + regulator-name = "VDD_1V8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + buck6: BUCK6 { + regulator-name = "NVCC_DRAM_1V35"; + regulator-min-microvolt = <1350000>; + regulator-max-microvolt = <1350000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo1: LDO1 { + regulator-name = "NVCC_SNVS_1V8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo2: LDO2 { + regulator-name = "VDD_SNVS_0V8"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <800000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo3: LDO3 { + regulator-name = "VDDA_1V8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo4: LDO4 { + regulator-name = "VDD_PHY_1V2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo5: LDO5 { + regulator-name = "NVCC_SD2"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + }; + }; +};