From patchwork Mon Apr 25 11:37:05 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Pali_Roh=C3=A1r?= X-Patchwork-Id: 12825615 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 9574FC433F5 for ; Mon, 25 Apr 2022 11:39:06 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:Message-Id:Date:Subject:Cc :To:From:Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:In-Reply-To:References: List-Owner; bh=FKH56ZCy2oQ16U0+awk/K5CWB7GcrvyrvSb01MWN2m4=; b=4m7GNgjmoGwlXe Eh348t8v8vOqE83+HO7161JrC5Z9Mu79geIONLBvscYWLZWJsU4AIyiyc1Fuz1KrFo0DuC8oI8Xl2 9MIzN3bD5O8Oix6ihAU6ogGKlEAWK2GnEEmCB1pUOZUTr/5lsDIc482P78i5YT4sG4pSpTYEIn7at akjUeOIJbBamspeELNfLEqT7PYkFPsRpbFFGtCDIEuKeyz92HzUaw9eYeZ6RwDNSVQn7y/z/KOjN7 6/jlArRPU9s03EffKx0SMF0cVomg/RaTcoxYOoezX//x7x5134mDDCn91wY/5AMdLRtINijwvM3lF fLPAKvK3VxyEsNCKYy+w==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1nix2e-009JGl-ON; Mon, 25 Apr 2022 11:38:08 +0000 Received: from ams.source.kernel.org ([2604:1380:4601:e00::1]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1nix2T-009JE9-PV for linux-arm-kernel@lists.infradead.org; Mon, 25 Apr 2022 11:37:59 +0000 Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ams.source.kernel.org (Postfix) with ESMTPS id D69EEB8128F; Mon, 25 Apr 2022 11:37:53 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 77DEBC385A7; Mon, 25 Apr 2022 11:37:52 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1650886672; bh=7h3ha01iKrve+RU9wcrPWPSP0bROV5CrSg/3niiwVbc=; h=From:To:Cc:Subject:Date:From; b=HwrLXtpx6yfaiP5sNx363mun1Ja2V01rRSIHAjHiziqsuylrAOAZMxiavmucoERJ3 tSIBfp65eWfDvZCRaF/RL5xnE/NG4gSyOb2y1p11xkhYTbKRQRIm10yEx0SNfkJRzL RSA6aZOQLl6NGTAvRoB/wFuQArygi7d5bx6QkTnblxYM6gx8mqDql7mC2tpkUdD3O7 nlOUNVr7rIhUamjkS+pxdhj+w6Vjp6zlKAUB2LM5xdIwIr57K2Xz8KgO2CsDeCdMOu qCQidebpWn3Vua2rCwvHQAw15urBfCS1P1vWTd23qYgGJrLUkVS4FHvI5Fx1hubvu4 AfsTYWJKXx6Vw== Received: by pali.im (Postfix) id 7E2EF4A32; Mon, 25 Apr 2022 13:37:49 +0200 (CEST) From: =?utf-8?q?Pali_Roh=C3=A1r?= To: Andrew Lunn , Gregory Clement , Sebastian Hesselbarth , Thomas Gleixner , Marc Zyngier Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH 1/2] irqchip/armada-370-xp: Do not touch Performance Counter Overflow on A375, A38x, A39x Date: Mon, 25 Apr 2022 13:37:05 +0200 Message-Id: <20220425113706.29310-1-pali@kernel.org> X-Mailer: git-send-email 2.20.1 MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220425_043758_017233_8F6F192B X-CRM114-Status: GOOD ( 14.36 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Register ARMADA_370_XP_INT_FABRIC_MASK_OFFS is Armada 370 and XP specific and on new Armada platforms it has different meaning. It does not configure Performance Counter Overflow interrupt masking. So do not touch this register on non-A370/XP platforms (A375, A38x and A39x). Signed-off-by: Pali Rohár Cc: stable@vger.kernel.org Reviewed-by: Andrew Lunn --- drivers/irqchip/irq-armada-370-xp.c | 11 ++++++++++- 1 file changed, 10 insertions(+), 1 deletion(-) diff --git a/drivers/irqchip/irq-armada-370-xp.c b/drivers/irqchip/irq-armada-370-xp.c index 5b8d571c041d..1120084cba09 100644 --- a/drivers/irqchip/irq-armada-370-xp.c +++ b/drivers/irqchip/irq-armada-370-xp.c @@ -308,7 +308,16 @@ static inline int armada_370_xp_msi_init(struct device_node *node, static void armada_xp_mpic_perf_init(void) { - unsigned long cpuid = cpu_logical_map(smp_processor_id()); + unsigned long cpuid; + + /* + * This Performance Counter Overflow interrupt is specific for + * Armada 370 and XP. It is not available on Armada 375, 38x and 39x. + */ + if (!of_machine_is_compatible("marvell,armada-370-xp")) + return; + + cpuid = cpu_logical_map(smp_processor_id()); /* Enable Performance Counter Overflow interrupts */ writel(ARMADA_370_XP_INT_CAUSE_PERF(cpuid),