| Message ID | 20220426134106.242353-4-fparent@baylibre.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | arm64: dts: mediatek: mt8195-demo: Add more peripheral support | expand |
On Tue, 2022-04-26 at 15:41 +0200, Fabien Parent wrote: > From: Biao Huang <biao.huang@mediatek.com> > > This commit adds device node for mt8195 ethernet. > > Signed-off-by: Biao Huang <biao.huang@mediatek.com> > Signed-off-by: Fabien Parent <fparent@baylibre.com> > --- > This patch comes from > https://urldefense.com/v3/__https://lore.kernel.org/all/20211207015505.16746-7-biao.huang@mediatek.com/__;!!CTRNKA9wMg0ARbw!zMbdbHaOYVgzrhlWiTJyY40dCmVZaK1jStklyKdY5qoDUoA5uoISlYOx9E801CRuEHQ$ > > > The differences between that patch and this patch is that: > * The EVB dts modification has been split into its own commit > * The patch was rebased to fix merge conflict with the upstream > mt8195.dtsi file > * Re-ordered the node to be correctly sorted based on node address > > arch/arm64/boot/dts/mediatek/mt8195.dtsi | 70 > ++++++++++++++++++++++++ > 1 file changed, 70 insertions(+) > > diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi > b/arch/arm64/boot/dts/mediatek/mt8195.dtsi > index aa05071a80b8..a58641d1cab0 100644 > --- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi > +++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi > @@ -912,6 +912,76 @@ spis1: spi@1101e000 { > status = "disabled"; > }; > > + eth: ethernet@11021000 { > + compatible = "mediatek,mt8195-gmac", > "snps,dwmac-5.10a"; > + reg = <0 0x11021000 0 0x4000>; > + interrupts = <GIC_SPI 716 IRQ_TYPE_LEVEL_HIGH > 0>; > + interrupt-names = "macirq"; > + mac-address = [00 55 7b b5 7d f7]; > + clock-names = "axi", > + "apb", > + "mac_main", > + "ptp_ref", > + "rmii_internal", > + "mac_cg"; > + clocks = <&pericfg_ao CLK_PERI_AO_ETHERNET>, > + <&pericfg_ao > CLK_PERI_AO_ETHERNET_BUS>, > + <&topckgen CLK_TOP_SNPS_ETH_250M>, > + <&topckgen > CLK_TOP_SNPS_ETH_62P4M_PTP>, > + <&topckgen CLK_TOP_SNPS_ETH_50M_RMII>, > + <&pericfg_ao > CLK_PERI_AO_ETHERNET_MAC>; > + assigned-clocks = <&topckgen > CLK_TOP_SNPS_ETH_250M>, > + <&topckgen > CLK_TOP_SNPS_ETH_62P4M_PTP>, > + <&topckgen > CLK_TOP_SNPS_ETH_50M_RMII>; > + assigned-clock-parents = <&topckgen > CLK_TOP_ETHPLL_D2>, > + <&topckgen > CLK_TOP_ETHPLL_D8>, > + <&topckgen > CLK_TOP_ETHPLL_D10>; > + power-domains = <&spm > MT8195_POWER_DOMAIN_ETHER>; > + mediatek,pericfg = <&infracfg_ao>; > + snps,axi-config = <&stmmac_axi_setup>; > + snps,mtl-rx-config = <&mtl_rx_setup>; > + snps,mtl-tx-config = <&mtl_tx_setup>; > + snps,txpbl = <16>; > + snps,rxpbl = <16>; > + clk_csr = <0>; > + status = "disabled"; > + > + stmmac_axi_setup: stmmac-axi-config { > + snps,wr_osr_lmt = <0x7>; > + snps,rd_osr_lmt = <0x7>; > + snps,blen = <0 0 0 0 16 8 4>; > + }; > + > + mtl_rx_setup: rx-queues-config { > + snps,rx-queues-to-use = <1>; > + snps,rx-sched-sp; > + queue0 { > + snps,dcb-algorithm; > + snps,map-to-dma-channel = > <0x0>; > + snps,priority = <0x0>; > + }; > + }; > + mtl_tx_setup: tx-queues-config { > + snps,tx-queues-to-use = <3>; > + snps,tx-sched-wrr; > + queue0 { > + snps,weight = <0x10>; > + snps,dcb-algorithm; > + snps,priority = <0x0>; > + }; > + queue1 { > + snps,weight = <0x11>; > + snps,dcb-algorithm; > + snps,priority = <0x1>; > + }; > + queue2 { > + snps,weight = <0x12>; > + snps,dcb-algorithm; > + snps,priority = <0x2>; > + }; > + }; > + }; > + > ssusb: usb@11201000 { > compatible ="mediatek,mt8195-mtu3", > "mediatek,mtu3"; > reg = <0 0x11201000 0 0x2dff>, Reviewed-by: Macpaul Lin <macpaul.lin@mediatek.com> Regards, Macpaul Lin
diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi index aa05071a80b8..a58641d1cab0 100644 --- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi @@ -912,6 +912,76 @@ spis1: spi@1101e000 { status = "disabled"; }; + eth: ethernet@11021000 { + compatible = "mediatek,mt8195-gmac", "snps,dwmac-5.10a"; + reg = <0 0x11021000 0 0x4000>; + interrupts = <GIC_SPI 716 IRQ_TYPE_LEVEL_HIGH 0>; + interrupt-names = "macirq"; + mac-address = [00 55 7b b5 7d f7]; + clock-names = "axi", + "apb", + "mac_main", + "ptp_ref", + "rmii_internal", + "mac_cg"; + clocks = <&pericfg_ao CLK_PERI_AO_ETHERNET>, + <&pericfg_ao CLK_PERI_AO_ETHERNET_BUS>, + <&topckgen CLK_TOP_SNPS_ETH_250M>, + <&topckgen CLK_TOP_SNPS_ETH_62P4M_PTP>, + <&topckgen CLK_TOP_SNPS_ETH_50M_RMII>, + <&pericfg_ao CLK_PERI_AO_ETHERNET_MAC>; + assigned-clocks = <&topckgen CLK_TOP_SNPS_ETH_250M>, + <&topckgen CLK_TOP_SNPS_ETH_62P4M_PTP>, + <&topckgen CLK_TOP_SNPS_ETH_50M_RMII>; + assigned-clock-parents = <&topckgen CLK_TOP_ETHPLL_D2>, + <&topckgen CLK_TOP_ETHPLL_D8>, + <&topckgen CLK_TOP_ETHPLL_D10>; + power-domains = <&spm MT8195_POWER_DOMAIN_ETHER>; + mediatek,pericfg = <&infracfg_ao>; + snps,axi-config = <&stmmac_axi_setup>; + snps,mtl-rx-config = <&mtl_rx_setup>; + snps,mtl-tx-config = <&mtl_tx_setup>; + snps,txpbl = <16>; + snps,rxpbl = <16>; + clk_csr = <0>; + status = "disabled"; + + stmmac_axi_setup: stmmac-axi-config { + snps,wr_osr_lmt = <0x7>; + snps,rd_osr_lmt = <0x7>; + snps,blen = <0 0 0 0 16 8 4>; + }; + + mtl_rx_setup: rx-queues-config { + snps,rx-queues-to-use = <1>; + snps,rx-sched-sp; + queue0 { + snps,dcb-algorithm; + snps,map-to-dma-channel = <0x0>; + snps,priority = <0x0>; + }; + }; + mtl_tx_setup: tx-queues-config { + snps,tx-queues-to-use = <3>; + snps,tx-sched-wrr; + queue0 { + snps,weight = <0x10>; + snps,dcb-algorithm; + snps,priority = <0x0>; + }; + queue1 { + snps,weight = <0x11>; + snps,dcb-algorithm; + snps,priority = <0x1>; + }; + queue2 { + snps,weight = <0x12>; + snps,dcb-algorithm; + snps,priority = <0x2>; + }; + }; + }; + ssusb: usb@11201000 { compatible ="mediatek,mt8195-mtu3", "mediatek,mtu3"; reg = <0 0x11201000 0 0x2dff>,