From patchwork Wed Apr 27 18:08:53 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kamal Dasu X-Patchwork-Id: 12829309 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 23F79C433EF for ; Wed, 27 Apr 2022 18:12:19 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:MIME-Version:List-Subscribe:List-Help: List-Post:List-Archive:List-Unsubscribe:List-Id:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=fym7iSggzoGxFYGx32tXoH7bCEinQEfQdL8E3bhe7EU=; b=JEHvKkHX4TIxJf LF1uSksF9bwB4O6uagKnQpCxKO0w3hhh+iZ9bLwkk2t3PZ7FhM/oer5xzBOlZio68LnCnhjbATLhL HbCfKtU9l8I0kkoxOqSttgFBPJu0ABonjp3MtEdEP7MjoTZb3qXupURNu//89a0N84RyLpwSRoeey ndI/gkoXuU8R9/oy3wRM3mYEUEXRSd621ipA6UrmGvc4tIZbMqCf9onfzCT9QVrBtgY/7ba31ZLXC YDpznoUPBoijX7MxDzDKJsRoifel+45ksM6Uotby/yw1QTYPxo1FwwSzx11EwuBKB5UEQY/ez71uy 6ynmoOzoAUHh1KqzoO6w==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1njm7s-002u4C-M6; Wed, 27 Apr 2022 18:10:56 +0000 Received: from mail-pf1-x433.google.com ([2607:f8b0:4864:20::433]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1njm6n-002tgj-Jw for linux-arm-kernel@lists.infradead.org; Wed, 27 Apr 2022 18:09:51 +0000 Received: by mail-pf1-x433.google.com with SMTP id a11so2245765pff.1 for ; Wed, 27 Apr 2022 11:09:49 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=SC7RZFmFzY1cOQBSZIdDAHzv/8LeJtBuHEGLtHlFN68=; b=qpzCGKxw/occv4Nuka8IWzq7q96NZjmWekn+OP2qa4Nty8SX7WF1zE1e1B4x4tRgVJ u0JTdGcftj7uwIBthE117rEBdHqeAvgTGr2ttmLNqOA5588saUD4H9aAQu7JlXhm5+eH hs5qn12hvTorb8EKjKqOGUUBAxWx3auU2HTA/uhSSvJlKoYse5hX0GszJc56Eb40zvg2 yy7vMUtAtscMZ4rNVhN5Paq0qM6mJjvasYgTUyC/oxLrxHUmTxxRmum1W1ZFffjqcOw6 40m03OPCHXL0aeMj3ypX0VYluGsePdF8UjTTJHmRVhIy7p55pSV9JllHexou656CxYFn oj2w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=SC7RZFmFzY1cOQBSZIdDAHzv/8LeJtBuHEGLtHlFN68=; b=n0iqRWl93vuFs5zRNB/LQ05TOjM3TSCVWXZYj28e0Thw/V28/XBc2z1Y0DSrXbkBHc qaaw+hZ9lNGzd2++RbAvRGuXi1KgEOSZCtOrHtweD6fNMd0tB5lWCofSXVLq6XI+3KOK 6i3l3RZ8Akaq4oldX6l3+4zLecdCpn372TQ01hufk6dyaXmSNrmZsfEOGd1wV8zYbdsr KyVvDdyhR7/swekfQAmq+gx/xQzxMjcgY5dh+SVGk6dNNFetgbuQAj15sJJu0RHYwjTb oap7LxYIPV8ZPgBhM4tu7IhosEYpyDEIhPy1o85LFbXBNWvUSmlZo10Fq5ui4D10aJkd QPbw== X-Gm-Message-State: AOAM531klqDWYk6GTsfmKTH9btdG/66ISn7FPBbRZmupgvpzeZSWPfLo gbDsTi7RnIqLKRHmwOfw7RQ= X-Google-Smtp-Source: ABdhPJyBfRvQK5ucNiOqjWVZwaDGd2EDnvC4GpPivMyaWL78F9cq64AYIKfXWqGw7aWexrgMeOqF6g== X-Received: by 2002:a63:4f0b:0:b0:3a9:f4ad:6c30 with SMTP id d11-20020a634f0b000000b003a9f4ad6c30mr24900316pgb.88.1651082989059; Wed, 27 Apr 2022 11:09:49 -0700 (PDT) Received: from mail.broadcom.net ([192.19.11.250]) by smtp.gmail.com with ESMTPSA id u25-20020aa78399000000b00505f75651e7sm19076859pfm.158.2022.04.27.11.09.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 27 Apr 2022 11:09:48 -0700 (PDT) From: Kamal Dasu To: ulf.hansson@linaro.org, robh+dt@kernel.org, krzk+dt@kernel.org, alcooperx@gmail.com Cc: f.fainelli@gmail.com, bcm-kernel-feedback-list@broadcom.com, adrian.hunter@intel.com, linux-mmc@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Kamal Dasu Subject: [PATCH v2 4/4] mmc: sdhci-brcmstb: Add ability to increase max clock rate for 72116b0 Date: Wed, 27 Apr 2022 14:08:53 -0400 Message-Id: <20220427180853.35970-5-kdasu.kdev@gmail.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20220427180853.35970-1-kdasu.kdev@gmail.com> References: <20220427180853.35970-1-kdasu.kdev@gmail.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220427_110949_691466_68A7FC4E X-CRM114-Status: GOOD ( 17.14 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org From: Al Cooper The 72116B0 has improved SDIO controllers that allow the max clock rate to be increased from a max of 100MHz to a max of 150MHz. The driver will need to get the clock and increase it's default rate and override the caps register, that still indicates a max of 100MHz. The new clock will be named "sdio_freq" in the DT node's "clock-names" list. The driver will use a DT property, "clock-frequency", to enable this functionality and will get the actual rate in MHz from the property to allow various speeds to be requested. Signed-off-by: Al Cooper Signed-off-by: Kamal Dasu --- drivers/mmc/host/sdhci-brcmstb.c | 25 +++++++++++++++++++++++++ 1 file changed, 25 insertions(+) diff --git a/drivers/mmc/host/sdhci-brcmstb.c b/drivers/mmc/host/sdhci-brcmstb.c index 683d0c685748..51a23e9f4535 100644 --- a/drivers/mmc/host/sdhci-brcmstb.c +++ b/drivers/mmc/host/sdhci-brcmstb.c @@ -250,6 +250,7 @@ static int sdhci_brcmstb_probe(struct platform_device *pdev) struct sdhci_pltfm_host *pltfm_host; const struct of_device_id *match; struct sdhci_brcmstb_priv *priv; + u32 base_clock_hz = 0; struct sdhci_host *host; struct resource *iomem; struct clk *clk; @@ -330,6 +331,30 @@ static int sdhci_brcmstb_probe(struct platform_device *pdev) if (match_priv->flags & BRCMSTB_MATCH_FLAGS_BROKEN_TIMEOUT) host->quirks |= SDHCI_QUIRK_BROKEN_TIMEOUT_VAL; + /* Change the base clock frequency if the DT property exists */ + if (device_property_read_u32(&pdev->dev, "max-frequency", + &base_clock_hz) == 0) { + struct clk *master_clk; + u32 actual_clock_mhz; + + master_clk = devm_clk_get(&pdev->dev, "sdio_freq"); + if (IS_ERR(master_clk)) { + dev_warn(&pdev->dev, + "Clock for \"sdio_freq\" was not found\n"); + } else { + clk_set_rate(master_clk, base_clock_hz); + actual_clock_mhz = clk_get_rate(master_clk) / 1000000; + + host->caps &= ~SDHCI_CLOCK_V3_BASE_MASK; + host->caps |= + (actual_clock_mhz << SDHCI_CLOCK_BASE_SHIFT); + /* Disable presets because they are now incorrect */ + host->quirks2 |= SDHCI_QUIRK2_PRESET_VALUE_BROKEN; + dev_dbg(&pdev->dev, + "Base Clock Frequency changed to %dMHz\n", + actual_clock_mhz); + } + } res = sdhci_brcmstb_add_host(host, priv); if (res) goto err;