diff mbox series

drivers/perf: arm_spe: Expose saturating counter to 16-bit

Message ID 20220429063307.63251-1-zhangshaokun@hisilicon.com (mailing list archive)
State New, archived
Headers show
Series drivers/perf: arm_spe: Expose saturating counter to 16-bit | expand

Commit Message

Shaokun Zhang April 29, 2022, 6:33 a.m. UTC
In order to acquire more accurate latency, Armv8.8[1] has defined the
CountSize field to 16-bit saturating counters when it's 0b0011.

Let's support this new feature and expose its to user under sysfs.

[1] https://developer.arm.com/documentation/ddi0487/latest

Cc: Will Deacon <will@kernel.org>
Cc: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Shaokun Zhang <zhangshaokun@hisilicon.com>
---
 drivers/perf/arm_spe_pmu.c | 3 +++
 1 file changed, 3 insertions(+)

Comments

Will Deacon May 6, 2022, 2:43 p.m. UTC | #1
On Fri, 29 Apr 2022 14:33:07 +0800, Shaokun Zhang wrote:
> In order to acquire more accurate latency, Armv8.8[1] has defined the
> CountSize field to 16-bit saturating counters when it's 0b0011.
> 
> Let's support this new feature and expose its to user under sysfs.
> 
> [1] https://developer.arm.com/documentation/ddi0487/latest
> 
> [...]

Applied to will (for-next/perf), thanks!

[1/1] drivers/perf: arm_spe: Expose saturating counter to 16-bit
      https://git.kernel.org/will/c/47a9ed88a4fc

Cheers,
diff mbox series

Patch

diff --git a/drivers/perf/arm_spe_pmu.c b/drivers/perf/arm_spe_pmu.c
index d44bcc29d99c..db670b265897 100644
--- a/drivers/perf/arm_spe_pmu.c
+++ b/drivers/perf/arm_spe_pmu.c
@@ -1035,6 +1035,9 @@  static void __arm_spe_pmu_dev_probe(void *info)
 		fallthrough;
 	case 2:
 		spe_pmu->counter_sz = 12;
+		break;
+	case 3:
+		spe_pmu->counter_sz = 16;
 	}
 
 	dev_info(dev,