From patchwork Tue May 3 09:38:48 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?b?UmV4LUJDIENoZW4gKOmZs+afj+i+sCk=?= X-Patchwork-Id: 12835468 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 1B8DCC433EF for ; Tue, 3 May 2022 09:46:05 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:CC:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=EG6ueKhRkhfSKAPVXCODXtGUXC0vhXdzex9zmUXH54s=; b=KugEtqS6CXG3fz HmLqeE+WcU5SvKHCxNT7Adm9lPR/cnPZSnA0hanxf1ltppXztmyhl1QN4gcU+8i83HMupSiAM6cGB nRL+1ghaXZ1b6FxN+ZXuDiL88rFYEshxrlDppel9pz3fY8c9D3mQKKkxviHtvMePObm3G6KQfCiuG nIJh5rjc6GS5rGBLRrn09J9GsSrXEwRv8PBs9N+cP3BTCrSv/VvRca3QjndaeMveUMCIs0q09HGRa Fyw5VcXRma3EFuPtsWHphRaRY4FW+RCGQJAx/ZR3EuZetF8Zq8PbFl0VkSzWUptukmcAiIskENDdg B1TKN6fizKIdTNgQ/BnA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1nlp5F-004tgQ-2A; Tue, 03 May 2022 09:44:41 +0000 Received: from mailgw01.mediatek.com ([216.200.240.184]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1nlp02-004qGR-6Q; Tue, 03 May 2022 09:39:19 +0000 X-UUID: 687b7d447b164b9d8246a924737af22c-20220503 X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.4, REQID:eb4ecfd3-6c45-4779-a433-cf72df921e17, OB:0, LO B:0,IP:0,URL:0,TC:0,Content:-20,EDM:0,RT:0,SF:0,FILE:0,RULE:Release_Ham,AC TION:release,TS:-20 X-CID-META: VersionHash:faefae9, CLOUDID:64f54fc7-85ee-4ac1-ac05-bd3f1e72e732, C OID:IGNORED,Recheck:0,SF:nil,TC:nil,Content:0,EDM:-3,File:nil,QS:0,BEC:nil X-UUID: 687b7d447b164b9d8246a924737af22c-20220503 Received: from mtkcas68.mediatek.inc [(172.29.94.19)] by mailgw01.mediatek.com (envelope-from ) (musrelay.mediatek.com ESMTP with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 334591027; Tue, 03 May 2022 02:39:02 -0700 Received: from mtkmbs11n2.mediatek.inc (172.21.101.187) by MTKMBS62DR.mediatek.inc (172.29.94.18) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Tue, 3 May 2022 02:39:01 -0700 Received: from mtkmbs11n2.mediatek.inc (172.21.101.187) by mtkmbs11n2.mediatek.inc (172.21.101.187) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.792.3; Tue, 3 May 2022 17:38:59 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs11n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.792.3 via Frontend Transport; Tue, 3 May 2022 17:38:59 +0800 From: Rex-BC Chen To: , , , , CC: , , , , , , , , , , , Rex-BC Chen Subject: [PATCH v6 08/16] clk: mediatek: reset: Support inuput argument index mode Date: Tue, 3 May 2022 17:38:48 +0800 Message-ID: <20220503093856.22250-9-rex-bc.chen@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20220503093856.22250-1-rex-bc.chen@mediatek.com> References: <20220503093856.22250-1-rex-bc.chen@mediatek.com> MIME-Version: 1.0 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220503_023918_314940_8E66E96C X-CRM114-Status: GOOD ( 19.57 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org There is a large number of mediatek infra reset bits, but we do not use all of them. In addition, the proper input argement of reset controller soulde be index. Therefore, to be compatible with previous drivers and usage, we add description variables to store the ids which can mapping to index. To use this mode, we need to put the id in rst_idx_map to map from index to ids. For example, if we want to input index 1 (this index is used to set bank 1 bit 14) for svs, we need to declare the reset controller like this: In drivers: static u16 rst_ofs[] = { 0x120, 0x130, 0x140, 0x150, 0x730, }; static u16 rst_idx_map[] = { 0 * 32 + 0, 1 * 32 + 14, .... }; static const struct mtk_clk_rst_desc clk_rst_desc = { .version = MTK_RST_SET_CLR, .rst_bank_ofs = rst_ofs, .rst_bank_nr = ARRAY_SIZE(rst_ofs), .rst_idx_map = rst_idx_map, .rst_idx_map_nr = ARRAY_SIZE(rst_idx_map), }; In dts: svs: { ... resets = <&infra 1>; ... }; Signed-off-by: Rex-BC Chen Reviewed-by: AngeloGioacchino Del Regno --- drivers/clk/mediatek/reset.c | 21 ++++++++++++++++++++- drivers/clk/mediatek/reset.h | 5 +++++ 2 files changed, 25 insertions(+), 1 deletion(-) diff --git a/drivers/clk/mediatek/reset.c b/drivers/clk/mediatek/reset.c index 11b2f74f121d..89e617ea6393 100644 --- a/drivers/clk/mediatek/reset.c +++ b/drivers/clk/mediatek/reset.c @@ -98,6 +98,18 @@ static const struct reset_control_ops mtk_reset_ops_set_clr = { .reset = mtk_reset_set_clr, }; +static int reset_xlate(struct reset_controller_dev *rcdev, + const struct of_phandle_args *reset_spec) +{ + struct mtk_clk_rst_data *data = to_mtk_clk_rst_data(rcdev); + + if (reset_spec->args[0] >= rcdev->nr_resets || + reset_spec->args[0] >= data->desc->rst_idx_map_nr) + return -EINVAL; + + return data->desc->rst_idx_map[reset_spec->args[0]]; +} + void mtk_register_reset_controller(struct device_node *np, const struct mtk_clk_rst_desc *desc) { @@ -136,10 +148,17 @@ void mtk_register_reset_controller(struct device_node *np, data->desc = desc; data->regmap = regmap; data->rcdev.owner = THIS_MODULE; - data->rcdev.nr_resets = desc->rst_bank_nr * RST_NR_PER_BANK; data->rcdev.ops = rcops; data->rcdev.of_node = np; + if (data->desc->rst_idx_map_nr > 0) { + data->rcdev.of_reset_n_cells = 1; + data->rcdev.nr_resets = desc->rst_idx_map_nr; + data->rcdev.of_xlate = reset_xlate; + } else { + data->rcdev.nr_resets = desc->rst_bank_nr * RST_NR_PER_BANK; + } + ret = reset_controller_register(&data->rcdev); if (ret) { pr_err("could not register reset controller: %d\n", ret); diff --git a/drivers/clk/mediatek/reset.h b/drivers/clk/mediatek/reset.h index 482df8012c5c..47635d964c69 100644 --- a/drivers/clk/mediatek/reset.h +++ b/drivers/clk/mediatek/reset.h @@ -28,11 +28,16 @@ enum mtk_reset_version { * @version: Reset version which is defined in enum mtk_reset_version. * @rst_bank_ofs: Pointer to an array containing base offsets of the reset register. * @rst_bank_nr: Quantity of reset bank. + * @rst_idx_map:Pointer to an array containing ids if input argument is index. + * This array is not necessary if our input argument does not mean index. + * @rst_idx_map_nr: Quantity of reset index map. */ struct mtk_clk_rst_desc { u8 version; u16 *rst_bank_ofs; u32 rst_bank_nr; + u16 *rst_idx_map; + u32 rst_idx_map_nr; }; /**