From patchwork Wed May 4 13:06:15 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Valentin Caron X-Patchwork-Id: 12837913 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id D8DA5C433EF for ; Wed, 4 May 2022 13:11:47 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:CC:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=U3GN0CSkFoGHEYkeCGEY82cDVKKIlmXcUu5hryE4954=; b=tHHwL4k8SATNdD Pb2ud7GQXjxguaOWEMAGLjhtlddiO41BiJ+rP8x0EXtk+nY20t17tJWNYIPzZhJ2tyy02p3MQLhTU Zk1j4nZNkP9H5+A6oMp3gS0+y+xI0o3yMFrt7hISXM29GhYIcjJ02kjOAGTh1FF+/nHWSwgsp+/FU 266vTIX4wFkaK4EdZ2DSNVsGhuV6eKodZve6XqadJXmdG9Boui6vh2IL+4ooPucwlDrWtyFacfA0e t18E1NG5eh9MLgVnNxezrOK0m7VKOzm0quLdUs2aPjXUp7s5JoghkI3JEOC6MiZmmRp4Wrkdkyb0f +TXlXEXr5r65TAg5TnUQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1nmEm9-00Ax6f-Iv; Wed, 04 May 2022 13:10:41 +0000 Received: from mx08-00178001.pphosted.com ([91.207.212.93] helo=mx07-00178001.pphosted.com) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1nmEiQ-00Aunc-Bn for linux-arm-kernel@lists.infradead.org; Wed, 04 May 2022 13:06:52 +0000 Received: from pps.filterd (m0046660.ppops.net [127.0.0.1]) by mx07-00178001.pphosted.com (8.17.1.5/8.17.1.5) with ESMTP id 244AIcL7026474; Wed, 4 May 2022 15:06:39 +0200 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=foss.st.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=selector1; bh=i160vd3SYJnXlFBbcmO1jrB6imf8Y/vVEsSy9dgKnng=; b=sK2kW1PK5X6qbZyiQZY66lDrImimdWnBeL31H1Nn0imk804FiE4BVZWizxQQydYBpE4l Ex+mTef2K/OcaNzVaDbObwPoSaALY8uusYsRRT2go74WZ5LVfi7V26QSZHEmLY6S2tiT tsedHAMkYFeiMhAlqnbEkYVpVMk5PaUk21Rl5+fNwOx1J4n8XzBn0tV4dNgC6XFl8LV4 47F1GHqb8p3g8qe02E505mMxnKxmFGSSHjqCXJRAD1smeC3lGcLsU9tkixS4h1auEpcY 9YemV5SLIVjCL18Ev9al416ccmyje1aucpm5DueReRds6cD8z7qTJ4l/fmlYMqN3RBcA Tw== Received: from beta.dmz-eu.st.com (beta.dmz-eu.st.com [164.129.1.35]) by mx07-00178001.pphosted.com (PPS) with ESMTPS id 3frt88wq4x-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 04 May 2022 15:06:39 +0200 Received: from euls16034.sgp.st.com (euls16034.sgp.st.com [10.75.44.20]) by beta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 98CA810002A; Wed, 4 May 2022 15:06:38 +0200 (CEST) Received: from Webmail-eu.st.com (sfhdag2node2.st.com [10.75.127.5]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id 91BCB21FEAA; Wed, 4 May 2022 15:06:38 +0200 (CEST) Received: from localhost (10.75.127.45) by SFHDAG2NODE2.st.com (10.75.127.5) with Microsoft SMTP Server (TLS) id 15.0.1497.26; Wed, 4 May 2022 15:06:37 +0200 From: Valentin Caron To: Alessandro Zummo , Alexandre Belloni , Rob Herring , Krzysztof Kozlowski , Alexandre Torgue CC: Gabriel Fernandez , Amelie Delaunay , Valentin Caron , , , , , Subject: [PATCH 4/6] rtc: stm32: add alarm A out feature Date: Wed, 4 May 2022 15:06:15 +0200 Message-ID: <20220504130617.331290-3-valentin.caron@foss.st.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220504130233.330983-1-valentin.caron@foss.st.com> References: <20220504130233.330983-1-valentin.caron@foss.st.com> MIME-Version: 1.0 X-Originating-IP: [10.75.127.45] X-ClientProxiedBy: SFHDAG2NODE2.st.com (10.75.127.5) To SFHDAG2NODE2.st.com (10.75.127.5) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.858,Hydra:6.0.486,FMLib:17.11.64.514 definitions=2022-05-04_04,2022-05-04_01,2022-02-23_01 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220504_060650_768019_F3E87DBE X-CRM114-Status: GOOD ( 23.77 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org STM32 RTC can pulse some SOC pins when an RTC alarm expires. This patch adds this functionality for alarm A. The pulse can out on three pins RTC_OUT1, RTC_OUT2, RTC_OUT2_RMP (PC13, PB2, PI8 on stm32mp15) (PC13, PB2, PI1 on stm32mp13). This patch only adds the functionality for devices which are using st,stm32mp1-rtc compatible. Signed-off-by: Valentin Caron --- drivers/rtc/rtc-stm32.c | 77 +++++++++++++++++++++++++++++++++++++++++ 1 file changed, 77 insertions(+) diff --git a/drivers/rtc/rtc-stm32.c b/drivers/rtc/rtc-stm32.c index ace041eb44b8..f27927be20b2 100644 --- a/drivers/rtc/rtc-stm32.c +++ b/drivers/rtc/rtc-stm32.c @@ -5,6 +5,7 @@ */ #include +#include #include #include #include @@ -44,8 +45,10 @@ #define STM32_RTC_CR_ALRAIE BIT(12) #define STM32_RTC_CR_COSEL BIT(19) #define STM32_RTC_CR_OSEL GENMASK(22, 21) +#define STM32_RTC_CR_OSEL_ALARM_A FIELD_PREP(STM32_RTC_CR_OSEL, 0x01) #define STM32_RTC_CR_COE BIT(23) #define STM32_RTC_CR_TAMPOE BIT(26) +#define STM32_RTC_CR_TAMPALRM_TYPE BIT(30) #define STM32_RTC_CR_OUT2EN BIT(31) /* STM32_RTC_ISR/STM32_RTC_ICSR bit fields */ @@ -134,6 +137,7 @@ struct stm32_rtc_data { bool need_dbp; bool has_wakeirq; bool has_lsco; + bool has_alarm_out; }; struct stm32_rtc { @@ -149,6 +153,7 @@ struct stm32_rtc { int wakeirq_alarm; int lsco; struct clk *clk_lsco; + int out_alarm; }; /* @@ -253,6 +258,64 @@ static void stm32_rtc_clk_lsco_disable(struct platform_device *pdev) writel_relaxed(cfgr &= ~STM32_RTC_CFGR_LSCOEN, rtc->base + regs.cfgr); } +static int stm32_rtc_out_alarm_config(struct platform_device *pdev) +{ + struct stm32_rtc *rtc = platform_get_drvdata(pdev); + struct stm32_rtc_registers regs = rtc->data->regs; + unsigned int cr = readl_relaxed(rtc->base + regs.cr); + unsigned int cfgr = readl_relaxed(rtc->base + regs.cfgr); + + cr &= ~STM32_RTC_CR_OSEL; + cr |= STM32_RTC_CR_OSEL_ALARM_A; + cr &= ~STM32_RTC_CR_TAMPOE; + cr &= ~STM32_RTC_CR_COE; + cr &= ~STM32_RTC_CR_TAMPALRM_TYPE; + + switch (rtc->out_alarm) { + case RTC_OUT1: + cr &= ~STM32_RTC_CR_OUT2EN; + cfgr &= ~STM32_RTC_CFGR_OUT2_RMP; + break; + case RTC_OUT2: + cr |= STM32_RTC_CR_OUT2EN; + cfgr &= ~STM32_RTC_CFGR_OUT2_RMP; + break; + case RTC_OUT2_RMP: + cr |= STM32_RTC_CR_OUT2EN; + cfgr |= STM32_RTC_CFGR_OUT2_RMP; + break; + default: + return -EINVAL; + } + + stm32_rtc_wpr_unlock(rtc); + writel_relaxed(cr, rtc->base + regs.cr); + writel_relaxed(cfgr, rtc->base + regs.cfgr); + stm32_rtc_wpr_lock(rtc); + + return 0; +} + +static void stm32_rtc_out_alarm_disable(struct platform_device *pdev) +{ + struct stm32_rtc *rtc = platform_get_drvdata(pdev); + struct stm32_rtc_registers regs = rtc->data->regs; + unsigned int cr = readl_relaxed(rtc->base + regs.cr); + unsigned int cfgr = readl_relaxed(rtc->base + regs.cfgr); + + cr &= ~STM32_RTC_CR_OSEL; + cr &= ~STM32_RTC_CR_TAMPOE; + cr &= ~STM32_RTC_CR_COE; + cr &= ~STM32_RTC_CR_TAMPALRM_TYPE; + cr &= ~STM32_RTC_CR_OUT2EN; + cfgr &= ~STM32_RTC_CFGR_OUT2_RMP; + + stm32_rtc_wpr_unlock(rtc); + writel_relaxed(cr, rtc->base + regs.cr); + writel_relaxed(cfgr, rtc->base + regs.cfgr); + stm32_rtc_wpr_lock(rtc); +} + static int stm32_rtc_enter_init_mode(struct stm32_rtc *rtc) { const struct stm32_rtc_registers *regs = &rtc->data->regs; @@ -657,6 +720,7 @@ static const struct stm32_rtc_data stm32_rtc_data = { .need_dbp = true, .has_wakeirq = false, .has_lsco = false, + .has_alarm_out = false, .regs = { .tr = 0x00, .dr = 0x04, @@ -681,6 +745,7 @@ static const struct stm32_rtc_data stm32h7_rtc_data = { .need_dbp = true, .has_wakeirq = false, .has_lsco = false, + .has_alarm_out = false, .regs = { .tr = 0x00, .dr = 0x04, @@ -714,6 +779,7 @@ static const struct stm32_rtc_data stm32mp1_data = { .need_dbp = false, .has_wakeirq = true, .has_lsco = true, + .has_alarm_out = true, .regs = { .tr = 0x00, .dr = 0x04, @@ -928,6 +994,17 @@ static int stm32_rtc_probe(struct platform_device *pdev) goto err; } + if (rtc->data->has_alarm_out) { + ret = of_property_read_s32(pdev->dev.of_node, "st,alarm", &rtc->out_alarm); + if (!ret) { + ret = stm32_rtc_out_alarm_config(pdev); + } else { + stm32_rtc_out_alarm_disable(pdev); + rtc->out_alarm = ret; + dev_dbg(&pdev->dev, "No alarm out: %d\n", ret); + } + } + if (rtc->data->has_lsco) { ret = of_property_read_s32(pdev->dev.of_node, "st,lsco", &rtc->lsco);