From patchwork Wed May 4 18:48:49 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ali Saidi X-Patchwork-Id: 12838397 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id E622CC433F5 for ; Wed, 4 May 2022 18:50:37 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:CC:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=Z4XbgmSZvbpiXAmchO7Qhdv553zM5Ft3Yam31Qk52ks=; b=IDTQkO2ulnejDZ KOBqyQmq/29H4sl3LPy+pKlkw49bW/DMM2cM26GNNkK2fYTK+meFkxHAJm5PLTLjigyDeUv7ehxzg Uq+BDKh1y8rrWjvQxhz6aH57AAM0zE2hXY0VkSaq6DkfOhQjnfprpgBw2pgMc2PgpF3AK2Uec0ic4 3PFjobJdayNiOozQ0iZ14C/3wPoPo2yg8WtnBcjIi8wYeBHOxZyySbiH5uzYh5+kfk83bcimb0Vjm WgZj0sv1XjfjRnfCdbSp+Q2QdB/vgYQSjVEGHTkisrh1K1KGYq+S2glymMO5QpXcLc0ar+6lbAR4u M70v7F5WIyHqmiW5okdQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1nmK3t-00CCs1-DB; Wed, 04 May 2022 18:49:21 +0000 Received: from smtp-fw-9103.amazon.com ([207.171.188.200]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1nmK3d-00CCkE-Jx for linux-arm-kernel@lists.infradead.org; Wed, 04 May 2022 18:49:08 +0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amazon.com; i=@amazon.com; q=dns/txt; s=amazon201209; t=1651690145; x=1683226145; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=Nyaq8rgExJohCmR7zMDXM3nviHVHqHiyIvnP+zDFzfs=; b=AZ+VS8XIKzUjZVYGaUmAka0TAw16C/ZFaZZVJkyCoqaooFTMkBz7KaVN JN+WimcgUc2aUKWGumzNNfNhS3rsXKt3Hw1Vwc72bCPQNrPHT3kSy6HQN I3ikZ3zShzj+JRu2uMlISAQhmlTceoHtPs9+KlWZBaT/khtEKKFMWesis E=; X-IronPort-AV: E=Sophos;i="5.91,198,1647302400"; d="scan'208";a="1012911897" Received: from pdx4-co-svc-p1-lb2-vlan2.amazon.com (HELO email-inbound-relay-pdx-2c-b09ea7fa.us-west-2.amazon.com) ([10.25.36.210]) by smtp-border-fw-9103.sea19.amazon.com with ESMTP; 04 May 2022 18:49:04 +0000 Received: from EX13MTAUWB001.ant.amazon.com (pdx1-ws-svc-p6-lb9-vlan3.pdx.amazon.com [10.236.137.198]) by email-inbound-relay-pdx-2c-b09ea7fa.us-west-2.amazon.com (Postfix) with ESMTPS id 2812A41E00; Wed, 4 May 2022 18:49:04 +0000 (UTC) Received: from EX13D02UWB003.ant.amazon.com (10.43.161.48) by EX13MTAUWB001.ant.amazon.com (10.43.161.249) with Microsoft SMTP Server (TLS) id 15.0.1497.32; Wed, 4 May 2022 18:48:59 +0000 Received: from EX13MTAUEB002.ant.amazon.com (10.43.60.12) by EX13D02UWB003.ant.amazon.com (10.43.161.48) with Microsoft SMTP Server (TLS) id 15.0.1497.32; Wed, 4 May 2022 18:48:59 +0000 Received: from dev-dsk-alisaidi-1d-b9a0e636.us-east-1.amazon.com (172.19.181.128) by mail-relay.amazon.com (10.43.60.234) with Microsoft SMTP Server id 15.0.1497.32 via Frontend Transport; Wed, 4 May 2022 18:48:58 +0000 Received: by dev-dsk-alisaidi-1d-b9a0e636.us-east-1.amazon.com (Postfix, from userid 5131138) id 7970420CC; Wed, 4 May 2022 18:48:57 +0000 (UTC) From: Ali Saidi To: , , , , , CC: , , , , , , , , , , , , , , , Subject: [PATCH v8 4/5] perf arm-spe: Don't set data source if it's not a memory operation Date: Wed, 4 May 2022 18:48:49 +0000 Message-ID: <20220504184850.24986-5-alisaidi@amazon.com> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20220504184850.24986-1-alisaidi@amazon.com> References: <20220504184850.24986-1-alisaidi@amazon.com> MIME-Version: 1.0 Precedence: Bulk X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220504_114905_885424_2F8F0B61 X-CRM114-Status: GOOD ( 18.76 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org From: Leo Yan Except memory load and store operations, Arm SPE records also can support other operation types, bug when set the data source field the current code assumes a record is a either load operation or store operation, this leads to wrongly synthesize memory samples. This patch strictly checks the record operation type, it only sets data source only for the operation types ARM_SPE_LD and ARM_SPE_ST, otherwise, returns zero for data source. Therefore, we can synthesize memory samples only when data source is a non-zero value, the function arm_spe__is_memory_event() is useless and removed. Fixes: e55ed3423c1b ("perf arm-spe: Synthesize memory event") Signed-off-by: Leo Yan Reviewed-by: Ali Saidi Tested-by: Ali Saidi Reviewed-by: German Gomez --- tools/perf/util/arm-spe.c | 22 ++++++++-------------- 1 file changed, 8 insertions(+), 14 deletions(-) diff --git a/tools/perf/util/arm-spe.c b/tools/perf/util/arm-spe.c index d2b64e3f588b..e032efc03274 100644 --- a/tools/perf/util/arm-spe.c +++ b/tools/perf/util/arm-spe.c @@ -387,26 +387,16 @@ static int arm_spe__synth_instruction_sample(struct arm_spe_queue *speq, return arm_spe_deliver_synth_event(spe, speq, event, &sample); } -#define SPE_MEM_TYPE (ARM_SPE_L1D_ACCESS | ARM_SPE_L1D_MISS | \ - ARM_SPE_LLC_ACCESS | ARM_SPE_LLC_MISS | \ - ARM_SPE_REMOTE_ACCESS) - -static bool arm_spe__is_memory_event(enum arm_spe_sample_type type) -{ - if (type & SPE_MEM_TYPE) - return true; - - return false; -} - static u64 arm_spe__synth_data_source(const struct arm_spe_record *record) { union perf_mem_data_src data_src = { 0 }; if (record->op == ARM_SPE_LD) data_src.mem_op = PERF_MEM_OP_LOAD; - else + else if (record->op == ARM_SPE_ST) data_src.mem_op = PERF_MEM_OP_STORE; + else + return 0; if (record->type & (ARM_SPE_LLC_ACCESS | ARM_SPE_LLC_MISS)) { data_src.mem_lvl = PERF_MEM_LVL_L3; @@ -510,7 +500,11 @@ static int arm_spe_sample(struct arm_spe_queue *speq) return err; } - if (spe->sample_memory && arm_spe__is_memory_event(record->type)) { + /* + * When data_src is zero it means the record is not a memory operation, + * skip to synthesize memory sample for this case. + */ + if (spe->sample_memory && data_src) { err = arm_spe__synth_mem_sample(speq, spe->memory_id, data_src); if (err) return err;