From patchwork Tue May 17 02:03:25 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ali Saidi X-Patchwork-Id: 12851807 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 40EF2C433F5 for ; Tue, 17 May 2022 02:05:05 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:CC:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=Z4XbgmSZvbpiXAmchO7Qhdv553zM5Ft3Yam31Qk52ks=; b=3oejMyY/LZbiG7 vhbFu67glvIPvBuPdW1X2LHIqxcXQI2FNN26JFxje3MwpdQlfnUfQ9WwY0qkqFHR1g80XW/GdT6oZ nHyB4dkS0rs7yr2EMCC6g/cVQUycvuCfkMGVnFd1syROn6uyxhXNY78/ogbSOd/5HvvKf0DncVCIt JSDsGydPO4U/ENT2vAJzHCuQ9P5dUcKbfdI86GnCuPHXqJ1EQxwElSuKmAYAIFO+HuJuLLJ4qbMer psS57bAgBexmejxU+dFSfgRnkrhvcjOSM+2xqln+o84fyoBnKW9rTLOu36ouEJh2Zj1iC8ETWO+3n WNQPikB6u6s2a8S9varw==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1nqmZ9-00BDN2-5K; Tue, 17 May 2022 02:04:03 +0000 Received: from smtp-fw-9103.amazon.com ([207.171.188.200]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1nqmYn-00BDEc-NF for linux-arm-kernel@lists.infradead.org; Tue, 17 May 2022 02:03:43 +0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amazon.com; i=@amazon.com; q=dns/txt; s=amazon201209; t=1652753021; x=1684289021; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=Nyaq8rgExJohCmR7zMDXM3nviHVHqHiyIvnP+zDFzfs=; b=YkEZMbEkathnpLeyCouWhaRR9BljS4ktROQ/syA2vuGhg3xXU5SbrP3c vU83pUwTQIUe62zvDqmAo6WWHrdjyQlfRO7CxV0LS3XduzhEope/ArlxA oP4LlBMWU4WuXBf+5EnonO+A4MJuevDOrMPrzo++Ir4XhBDY/oJ3OfGAI Q=; X-IronPort-AV: E=Sophos;i="5.91,231,1647302400"; d="scan'208";a="1016240760" Received: from pdx4-co-svc-p1-lb2-vlan2.amazon.com (HELO email-inbound-relay-pdx-2c-51ba86d8.us-west-2.amazon.com) ([10.25.36.210]) by smtp-border-fw-9103.sea19.amazon.com with ESMTP; 17 May 2022 02:03:36 +0000 Received: from EX13MTAUWC002.ant.amazon.com (pdx1-ws-svc-p6-lb9-vlan2.pdx.amazon.com [10.236.137.194]) by email-inbound-relay-pdx-2c-51ba86d8.us-west-2.amazon.com (Postfix) with ESMTPS id A3C00C10C5; Tue, 17 May 2022 02:03:36 +0000 (UTC) Received: from EX13D02UWC003.ant.amazon.com (10.43.162.199) by EX13MTAUWC002.ant.amazon.com (10.43.162.240) with Microsoft SMTP Server (TLS) id 15.0.1497.32; Tue, 17 May 2022 02:03:34 +0000 Received: from EX13MTAUEA002.ant.amazon.com (10.43.61.77) by EX13D02UWC003.ant.amazon.com (10.43.162.199) with Microsoft SMTP Server (TLS) id 15.0.1497.32; Tue, 17 May 2022 02:03:34 +0000 Received: from dev-dsk-alisaidi-1d-b9a0e636.us-east-1.amazon.com (172.19.181.128) by mail-relay.amazon.com (10.43.61.169) with Microsoft SMTP Server id 15.0.1497.32 via Frontend Transport; Tue, 17 May 2022 02:03:33 +0000 Received: by dev-dsk-alisaidi-1d-b9a0e636.us-east-1.amazon.com (Postfix, from userid 5131138) id 987B52165; Tue, 17 May 2022 02:03:33 +0000 (UTC) From: Ali Saidi To: , , , , , CC: , , , , , , , , , , , , , , , Subject: [PATCH v9 4/5] perf arm-spe: Don't set data source if it's not a memory operation Date: Tue, 17 May 2022 02:03:25 +0000 Message-ID: <20220517020326.18580-5-alisaidi@amazon.com> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20220517020326.18580-1-alisaidi@amazon.com> References: <20220517020326.18580-1-alisaidi@amazon.com> MIME-Version: 1.0 Precedence: Bulk X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220516_190341_837122_36E7C2E3 X-CRM114-Status: GOOD ( 19.00 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org From: Leo Yan Except memory load and store operations, Arm SPE records also can support other operation types, bug when set the data source field the current code assumes a record is a either load operation or store operation, this leads to wrongly synthesize memory samples. This patch strictly checks the record operation type, it only sets data source only for the operation types ARM_SPE_LD and ARM_SPE_ST, otherwise, returns zero for data source. Therefore, we can synthesize memory samples only when data source is a non-zero value, the function arm_spe__is_memory_event() is useless and removed. Fixes: e55ed3423c1b ("perf arm-spe: Synthesize memory event") Signed-off-by: Leo Yan Reviewed-by: Ali Saidi Tested-by: Ali Saidi Reviewed-by: German Gomez --- tools/perf/util/arm-spe.c | 22 ++++++++-------------- 1 file changed, 8 insertions(+), 14 deletions(-) diff --git a/tools/perf/util/arm-spe.c b/tools/perf/util/arm-spe.c index d2b64e3f588b..e032efc03274 100644 --- a/tools/perf/util/arm-spe.c +++ b/tools/perf/util/arm-spe.c @@ -387,26 +387,16 @@ static int arm_spe__synth_instruction_sample(struct arm_spe_queue *speq, return arm_spe_deliver_synth_event(spe, speq, event, &sample); } -#define SPE_MEM_TYPE (ARM_SPE_L1D_ACCESS | ARM_SPE_L1D_MISS | \ - ARM_SPE_LLC_ACCESS | ARM_SPE_LLC_MISS | \ - ARM_SPE_REMOTE_ACCESS) - -static bool arm_spe__is_memory_event(enum arm_spe_sample_type type) -{ - if (type & SPE_MEM_TYPE) - return true; - - return false; -} - static u64 arm_spe__synth_data_source(const struct arm_spe_record *record) { union perf_mem_data_src data_src = { 0 }; if (record->op == ARM_SPE_LD) data_src.mem_op = PERF_MEM_OP_LOAD; - else + else if (record->op == ARM_SPE_ST) data_src.mem_op = PERF_MEM_OP_STORE; + else + return 0; if (record->type & (ARM_SPE_LLC_ACCESS | ARM_SPE_LLC_MISS)) { data_src.mem_lvl = PERF_MEM_LVL_L3; @@ -510,7 +500,11 @@ static int arm_spe_sample(struct arm_spe_queue *speq) return err; } - if (spe->sample_memory && arm_spe__is_memory_event(record->type)) { + /* + * When data_src is zero it means the record is not a memory operation, + * skip to synthesize memory sample for this case. + */ + if (spe->sample_memory && data_src) { err = arm_spe__synth_mem_sample(speq, spe->memory_id, data_src); if (err) return err;