From patchwork Tue May 17 11:07:36 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Ilpo_J=C3=A4rvinen?= X-Patchwork-Id: 12852296 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id DE2F7C433EF for ; Tue, 17 May 2022 11:09:59 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=z7ZwuDYCJetYWdO3FjeT1jd2/lCc0Rz7l2my/GrKPHM=; b=JT+LEcZn4K5dXh oAooqOdsFN7emTGkT3AhbJ+DI75lpj1zMsLr3M6H5FXvPeb1ujzEHmgoBoa43Jb8attFF0ZLlkK+w vCJBvZdxv4fFbk1MRb3Ti/PUy02Kdkh/2NsVbsgURp/MGdhVE5FYSuIV2AQD81EAC5EhVsjWm3L9w 72uECVNLE7wHWvVl+db5kSW2HjIgsPcIhWXsCqUcStjSo+VwN1H3JpEIGskCgxNyfXXej46oqB1jk uZ485FWWcvSXdC8dc+lJzGbHf/tHbveIfWwzwXTpDfJd/3tKBeo9rw4tF0QTeqYU6qrTNfFmjmP4u +UPVP5Hrgq5xFfVueAMA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1nqv4O-00DHqo-Uw; Tue, 17 May 2022 11:08:53 +0000 Received: from mga17.intel.com ([192.55.52.151]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1nqv3x-00DHVG-II for linux-arm-kernel@lists.infradead.org; Tue, 17 May 2022 11:08:26 +0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1652785705; x=1684321705; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=B/wsivre0Bc6qlbjo3she/qQCDt/pTlKU20VjyLCa68=; b=BG6hiY8acAju7sKaUALXT6bROQfAhPXQg8r1SIvJaQdA4nXmzxftiTGg bwN+bZ2hiWKjz1RslGvGnPm7tJx0dysqDPeZ9NG37L7evUSLHtlYjPmY4 yOCoC7oIHq8emOFu2lBu4RYSw7GAVC+GQsSxxRLVfofo35v7K0ftFkGMK 24+W4POrTsGfH/ExC1Mj+HwowbTOtH9nKcnAyHgXrtLXQ0qd4DaVqaJwY 5718a5/J7lQ9LnDMYn5mqypqn1LEj1f34fFdphUNOo9u4MV3FHsh/TnJw wNKHDqxUWV13jxmrlMVwAJUHY7Gqlomd3KPPy00kNxknQWcaydO4D4cwD w==; X-IronPort-AV: E=McAfee;i="6400,9594,10349"; a="251658959" X-IronPort-AV: E=Sophos;i="5.91,232,1647327600"; d="scan'208";a="251658959" Received: from orsmga007.jf.intel.com ([10.7.209.58]) by fmsmga107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 17 May 2022 04:08:25 -0700 X-IronPort-AV: E=Sophos;i="5.91,232,1647327600"; d="scan'208";a="568831136" Received: from mtarral-mobl.ger.corp.intel.com (HELO ijarvine-MOBL2.ger.corp.intel.com) ([10.252.52.88]) by orsmga007-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 17 May 2022 04:08:22 -0700 From: =?utf-8?q?Ilpo_J=C3=A4rvinen?= To: linux-serial@vger.kernel.org, Greg KH , Jiri Slaby , Maxime Coquelin , Alexandre Torgue , Erwan Le Ray , linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Cc: =?utf-8?q?Ilpo_J=C3=A4rvinen?= Subject: [PATCH 8/9] serial: stm32-usart: Correct CSIZE, bits, and parity Date: Tue, 17 May 2022 14:07:36 +0300 Message-Id: <20220517110737.37148-9-ilpo.jarvinen@linux.intel.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20220517110737.37148-1-ilpo.jarvinen@linux.intel.com> References: <20220517110737.37148-1-ilpo.jarvinen@linux.intel.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220517_040825_663772_5F8069A8 X-CRM114-Status: GOOD ( 10.74 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Add CSIZE sanitization for unsupported CSIZE configurations. In addition, if parity is asked for but CSx was unsupported, the sensible result is CS8+parity which requires setting USART_CR1_M0 like with 9 bits. Incorrect CSIZE results in miscalculation of the frame bits in tty_get_char_size() or in its predecessor where the roughly the same code is directly within uart_update_timeout(). Cc: Erwan Le Ray Fixes: c8a9d043947b (serial: stm32: fix word length configuration) Signed-off-by: Ilpo Järvinen --- drivers/tty/serial/stm32-usart.c | 15 ++++++++++++--- 1 file changed, 12 insertions(+), 3 deletions(-) diff --git a/drivers/tty/serial/stm32-usart.c b/drivers/tty/serial/stm32-usart.c index 87b5cd4c9743..3c551fd4f3ff 100644 --- a/drivers/tty/serial/stm32-usart.c +++ b/drivers/tty/serial/stm32-usart.c @@ -1037,13 +1037,22 @@ static void stm32_usart_set_termios(struct uart_port *port, * CS8 or (CS7 + parity), 8 bits word aka [M1:M0] = 0b00 * M0 and M1 already cleared by cr1 initialization. */ - if (bits == 9) + if (bits == 9) { cr1 |= USART_CR1_M0; - else if ((bits == 7) && cfg->has_7bits_data) + } else if ((bits == 7) && cfg->has_7bits_data) { cr1 |= USART_CR1_M1; - else if (bits != 8) + } else if (bits != 8) { dev_dbg(port->dev, "Unsupported data bits config: %u bits\n" , bits); + cflag &= ~CSIZE; + cflag |= CS8; + termios->c_cflag = cflag; + bits = 8; + if (cflag & PARENB) { + bits++; + cr1 |= USART_CR1_M0; + } + } if (ofs->rtor != UNDEF_REG && (stm32_port->rx_ch || (stm32_port->fifoen &&