From patchwork Tue May 17 12:58:21 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu Beznea X-Patchwork-Id: 12852463 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id CEE19C433EF for ; Tue, 17 May 2022 13:09:52 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:CC:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=hyEQ8zLGJfI5wBZc6xRY3wwsxnxpUtUaKOpqRe6QBew=; b=4BdYnxWK0df+Op RYaK72TTs0jRMZwy11WNajUI8LiRL0052LM+ua3uuOCdZduGa6FnN7mCMqNgeRhxn0GkaDL4cCG8C mk5vOtnsL1UMlfZ5j0rRufoLgOIEkol7Mk4i7ZlcYVVAvXx7z4CAaJMICkvt8foE/ob6/cqmAgmz5 VUeecix1mNU0LRI5odZgI1bYW6GJ2xxR0QyqFQBTvxKVRbMuJFVGxRLphsqet2lo/tONICXU9WNfw trTefTa4qcHNld/fTXWnZXxUA+cD2tamE/rymxaPdIh0ufclFO0Q3JuNdMAcm5Ty0XtO/MwO8bJdz QsXcSOnNKCbCMy1EC8Bw==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1nqwwK-00DndS-VG; Tue, 17 May 2022 13:08:41 +0000 Received: from esa.microchip.iphmx.com ([68.232.154.123]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1nqwmf-00DjDZ-Cb for linux-arm-kernel@lists.infradead.org; Tue, 17 May 2022 12:58:43 +0000 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1652792321; x=1684328321; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=ChdscaNYcNyAXcopz9BhhqP4M+pQrlts4cBNiLiQQeQ=; b=hu7r2NE7OjrMYLa42K01dBXIQ1HIb/2eqHPCoy8Td6vkKns6cNLtwoCK k+t46V4DolFnvJyQpdkxk1sXZEOSy0xRp7UtFKyD5hMy3sYdqyXpKJjvu etSRXeXDOArYRTVIv7NDNoIkpbCudVNRhchfspycWWHmB0gVGukwcxCV9 nX9bpAFhpIuJfPmfqGdvtDyqehlXVqY4waSZ81l+Z4WOEaxxew5LVVTHG QEfvp+t/thSn5vuHHE/Rez0pxtSPz1cFQ0vBGe0php/QxbYvSS1wnSeRt qZGIWG6eBeueoSIG7MlDZ3EtHUCblIS+Af6Ik9Jw7Z/pXRQmUmF5YI2fU A==; X-IronPort-AV: E=Sophos;i="5.91,232,1647327600"; d="scan'208";a="156388537" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa4.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 17 May 2022 05:58:37 -0700 Received: from chn-vm-ex01.mchp-main.com (10.10.85.143) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.17; Tue, 17 May 2022 05:58:36 -0700 Received: from ROB-ULT-M18063.microchip.com (10.10.115.15) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server id 15.1.2375.17 via Frontend Transport; Tue, 17 May 2022 05:58:34 -0700 From: Claudiu Beznea To: , , CC: , , , Claudiu Beznea Subject: [PATCH v2 1/2] dt-bindings: microchip-otpc: document Microchip OTPC Date: Tue, 17 May 2022 15:58:21 +0300 Message-ID: <20220517125822.579580-2-claudiu.beznea@microchip.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220517125822.579580-1-claudiu.beznea@microchip.com> References: <20220517125822.579580-1-claudiu.beznea@microchip.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220517_055841_552800_4AB71172 X-CRM114-Status: GOOD ( 12.95 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Document Microchip OTP controller. Signed-off-by: Claudiu Beznea --- .../nvmem/microchip-sama7g5,otpc.yaml | 50 +++++++++++++++++++ .../nvmem/microchip-sama7g5,otpc.h | 12 +++++ 2 files changed, 62 insertions(+) create mode 100644 Documentation/devicetree/bindings/nvmem/microchip-sama7g5,otpc.yaml create mode 040000 include/dt-bindings/nvmem create mode 100644 include/dt-bindings/nvmem/microchip-sama7g5,otpc.h diff --git a/Documentation/devicetree/bindings/nvmem/microchip-sama7g5,otpc.yaml b/Documentation/devicetree/bindings/nvmem/microchip-sama7g5,otpc.yaml new file mode 100644 index 000000000000..e0cbdd8a47aa --- /dev/null +++ b/Documentation/devicetree/bindings/nvmem/microchip-sama7g5,otpc.yaml @@ -0,0 +1,50 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/nvmem/microchip-sama7g5,otpc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Microchip SAMA7G5 OTP Controller (OTPC) + +maintainers: + - Claudiu Beznea + +description: | + OTP controller drives a NVMEM memory where system specific data + (e.g. calibration data for analog cells, hardware configuration + settings, chip identifiers) or user specific data could be stored. + +allOf: + - $ref: "nvmem.yaml#" + +properties: + compatible: + items: + - const: microchip,sama7g5-otpc + - const: syscon + + reg: + maxItems: 1 + +required: + - compatible + - reg + +unevaluatedProperties: false + +examples: + - | + #include + + otpc: efuse@e8c00000 { + compatible = "microchip,sama7g5-otpc", "syscon"; + reg = <0xe8c00000 0xec>; + #address-cells = <1>; + #size-cells = <1>; + + temperature_calib: calib@1 { + reg = ; + }; + }; + +... diff --git a/include/dt-bindings/nvmem/microchip-sama7g5,otpc.h b/include/dt-bindings/nvmem/microchip-sama7g5,otpc.h new file mode 100644 index 000000000000..f570b23165a2 --- /dev/null +++ b/include/dt-bindings/nvmem/microchip-sama7g5,otpc.h @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause */ + +#ifndef _DT_BINDINGS_NVMEM_MICROCHIP_OTPC_H +#define _DT_BINDINGS_NVMEM_MICROCHIP_OTPC_H + +/* + * Need to have it as a multiple of 4 as NVMEM memory is registered with + * stride = 4. + */ +#define OTP_PKT(id) ((id) * 4) + +#endif