From patchwork Mon May 23 09:33:42 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?UmV4LUJDIENoZW4gKOmZs+afj+i+sCk=?= X-Patchwork-Id: 12858867 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id C33C9C433FE for ; Mon, 23 May 2022 11:01:08 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:CC:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=9WMAP7Wuq7YNEORbYSst88jlLBxR50gvdtf8RHGjO3M=; b=Fnww2/6uEuesB7 BExtpC3Ov8jna4QXNgN1xlAeITAfqirajjfzTjCsd7GV8GzOdWikpsYt0qs6IOoY6FmmGcNt40/nl 588mb3BjB1v0Z2z0A76KgBREj4uwNSxHp32Xf45s9s0G/4EH78jHsyScM/953zXCvdzzPTa54xtHu Dlxt4v2K+bw7C3EvM8tVMVPdiIadEmBJ82K0S5GkLVycKRrl5Y3CqmiTIIWyXhqLN7MMCHZC6Fpb8 MfyrSgA4Rg9uDPD6059kS4sQTwOkMCucrXlSUpfvoTajpvYBMZ8KvnAJEngXQ/Go57+BCbGN6YMmq QSlfZukiXeG4ysQE7bgw==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1nt5my-003UBK-Jq; Mon, 23 May 2022 10:59:52 +0000 Received: from mailgw01.mediatek.com ([216.200.240.184]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1nt4bX-002wU7-TI; Mon, 23 May 2022 09:44:05 +0000 X-UUID: de2e8eb0ba3f4144bed2f2fe3c96ad3a-20220523 X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.5, REQID:d9db0599-ce4e-4feb-b796-2f9743472594, OB:0, LO B:0,IP:0,URL:0,TC:0,Content:0,EDM:0,RT:0,SF:0,FILE:0,RULE:Release_Ham,ACTI ON:release,TS:0 X-CID-META: VersionHash:2a19b09, CLOUDID:c45e487a-5ef6-470b-96c9-bdb8ced32786, C OID:IGNORED,Recheck:0,SF:nil,TC:nil,Content:0,EDM:-3,IP:nil,URL:0,File:nil ,QS:0,BEC:nil X-UUID: de2e8eb0ba3f4144bed2f2fe3c96ad3a-20220523 Received: from mtkcas66.mediatek.inc [(172.29.193.44)] by mailgw01.mediatek.com (envelope-from ) (musrelay.mediatek.com ESMTP with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 2132478203; Mon, 23 May 2022 02:43:52 -0700 Received: from mtkmbs11n1.mediatek.inc (172.21.101.185) by MTKMBS62DR.mediatek.inc (172.29.94.18) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Mon, 23 May 2022 02:33:51 -0700 Received: from mtkcas11.mediatek.inc (172.21.101.40) by mtkmbs11n1.mediatek.inc (172.21.101.185) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.2.792.3; Mon, 23 May 2022 17:33:50 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas11.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Mon, 23 May 2022 17:33:50 +0800 From: Rex-BC Chen To: , , , , CC: , , , , , , , , , , , , Rex-BC Chen Subject: [RESEND v8 15/19] arm64: dts: mediatek: Add infra #reset-cells property for MT8192 Date: Mon, 23 May 2022 17:33:42 +0800 Message-ID: <20220523093346.28493-16-rex-bc.chen@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20220523093346.28493-1-rex-bc.chen@mediatek.com> References: <20220523093346.28493-1-rex-bc.chen@mediatek.com> MIME-Version: 1.0 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220523_024400_016999_AC14C6B7 X-CRM114-Status: UNSURE ( 7.41 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org To support reset of infra, we add property of #reset-cells. Signed-off-by: Rex-BC Chen Reviewed-by: AngeloGioacchino Del Regno Reviewed-by: Nícolas F. R. A. Prado Tested-by: Nícolas F. R. A. Prado --- arch/arm64/boot/dts/mediatek/mt8192.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi index 733aec2e7f77..13ba5fee4afa 100644 --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi @@ -271,6 +271,7 @@ compatible = "mediatek,mt8192-infracfg", "syscon"; reg = <0 0x10001000 0 0x1000>; #clock-cells = <1>; + #reset-cells = <1>; }; pericfg: syscon@10003000 {