From patchwork Mon May 30 12:34:24 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Fabien Parent X-Patchwork-Id: 12864587 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 9BE29C433F5 for ; Mon, 30 May 2022 12:36:39 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:Message-Id:Date:Subject:Cc :To:From:Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:In-Reply-To:References: List-Owner; bh=Eidt8wrbk2qvA9D8totYjkug24e6DI+6VSCXnebY/S0=; b=ewjblwYINXHkWW o4sGfxU14MRzO0sPu9t7pf9duU8Eg/69Qkq2/bAOzIoxaKDHhTb1lDnRFF9X1KXekDAVroxitAVwO CrjKeGbppGrQ/Flbg8uksXbNCoueXFPlAEjXHJFvaZgW/kaWx9JQUL9fHC4Z3kkoWJQ1SAfO62VpB BxTqxGcw2CUjCaRB4WlPwWym4B1lOfwwrnPy3I+y2p/u91zHXJ7HCoYTxUGBZaPgCj1ttrx49fomU HyD2T9X8CkL+AwGieO3xmzq97TtaWuFcI9CR1rsRr02rFEOApfNsTNFs6qysQq1h8UWnM41vejcM4 5AqxawHdIMOh/Zi/S0vg==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1nvecG-006WTi-3G; Mon, 30 May 2022 12:35:24 +0000 Received: from mail-wr1-x431.google.com ([2a00:1450:4864:20::431]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1nveby-006WPq-1K for linux-arm-kernel@lists.infradead.org; Mon, 30 May 2022 12:35:13 +0000 Received: by mail-wr1-x431.google.com with SMTP id s24so7137719wrb.10 for ; Mon, 30 May 2022 05:35:03 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20210112.gappssmtp.com; s=20210112; h=from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=4ZpnujIPcolEhKbIJZUfooL6oIUs8mzgT5bxqd2OLwk=; b=civVMl7MXBedL2Fy/RdMR2hvoMq61sw/bSOuRyUnGfnpbQlu1B1vaETDk2eoLtMg61 xxvEM0CcGiuHnAv6EMTxHCVekfHJ443IW5HAHw1nPPodMQDAgQb/Z8wkdyR2n2oVdc02 rEchF77XObT5skBCADYM/9HeAkGoea+j9J1auHdrH25hfsrcuBh06zz0PQOUIkBpRAHo 9mlga4VSDuJ7sjz7UYdmr50MV3YV9+ezDISlXifrMQirUadM1ssMASjkx+97cXDUuyeb JhphSXc6/ervgN2b3jAzZSnPdDVaaUjM91vEkyX+Un5qEiD2lJPkDNrYMhf/x2hF+OXy 7cRQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=4ZpnujIPcolEhKbIJZUfooL6oIUs8mzgT5bxqd2OLwk=; b=GbEdMDyTRqIN695pKJYaOJpl88vPRN8PbaQDkLItPJSllObp0HNVDbMTkbFCsiYL3z eTPkFsWndjFMmn/M9BZQaive04NTTlan+UDYFF3Kxv9COvb56mybEaPVUoPgXkwACuNl 09skePKiDlu/FbSbGv/uc+nv7qdqeRGK63LXv7qqWl73xHG4gXPKr/ZD1MK1k//9l5wF WHa32bcCzKtFhi+1eEq903dBh5xPdoS2fK7LlVBl//Ye7s8CRC2mqRwARA0hush8BVlN S1jFi0zRrOJRJZ4rXHBM7EF3uh4wS+FezF2/HGUSxKF0C1ejlUrbcwEme52lF6CfPLcv waTQ== X-Gm-Message-State: AOAM531rMms5gNSf3Z93nRwhG0D/UPacdbu3gyZCxsRgZjThYgY24aGh aRouh6KYjL+9xVK4rXvvGG3H8Q== X-Google-Smtp-Source: ABdhPJxvnP7l8SO28NpVJS5NOclYzbNoRLMyWaTv8lhRa6I5+hFmHhKsWwpdaDK81i85ecqujt0hRA== X-Received: by 2002:a05:6000:1611:b0:210:28cc:65dd with SMTP id u17-20020a056000161100b0021028cc65ddmr8793920wrb.700.1653914102514; Mon, 30 May 2022 05:35:02 -0700 (PDT) Received: from helium.lan ([88.160.162.107]) by smtp.gmail.com with ESMTPSA id o3-20020a5d47c3000000b0020d0cdbf7eesm9380895wrc.111.2022.05.30.05.35.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 30 May 2022 05:35:01 -0700 (PDT) From: Fabien Parent To: Sean Wang , Linus Walleij , Matthias Brugger Cc: Fabien Parent , linux-mediatek@lists.infradead.org, linux-gpio@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH 1/2] pinctrl: mediatek: common: add quirk for broken set/clr modes Date: Mon, 30 May 2022 14:34:24 +0200 Message-Id: <20220530123425.689459-1-fparent@baylibre.com> X-Mailer: git-send-email 2.36.1 MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220530_053506_343167_728B485A X-CRM114-Status: GOOD ( 15.03 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On MT8365, the SET/CLR of the mode is broken and some pin modes won't be set correctly. Add a quirk for such SoCs, so that instead of using the SET/CLR register use the main R/W register to read/update/write the modes. Signed-off-by: Fabien Parent --- drivers/pinctrl/mediatek/pinctrl-mtk-common.c | 46 ++++++++++++------- drivers/pinctrl/mediatek/pinctrl-mtk-common.h | 3 ++ 2 files changed, 33 insertions(+), 16 deletions(-) diff --git a/drivers/pinctrl/mediatek/pinctrl-mtk-common.c b/drivers/pinctrl/mediatek/pinctrl-mtk-common.c index f25b3e09386b..156627d9c552 100644 --- a/drivers/pinctrl/mediatek/pinctrl-mtk-common.c +++ b/drivers/pinctrl/mediatek/pinctrl-mtk-common.c @@ -330,23 +330,37 @@ static int mtk_pconf_set_pull_select(struct mtk_pinctrl *pctl, return -EINVAL; } - bit = BIT(pin & pctl->devdata->mode_mask); - if (enable) - reg_pullen = SET_ADDR(mtk_get_port(pctl, pin) + - pctl->devdata->pullen_offset, pctl); - else - reg_pullen = CLR_ADDR(mtk_get_port(pctl, pin) + - pctl->devdata->pullen_offset, pctl); - - if (isup) - reg_pullsel = SET_ADDR(mtk_get_port(pctl, pin) + - pctl->devdata->pullsel_offset, pctl); - else - reg_pullsel = CLR_ADDR(mtk_get_port(pctl, pin) + - pctl->devdata->pullsel_offset, pctl); + if (pctl->devdata->quirks & MTK_PINCTRL_MODE_SET_CLR_BROKEN) { + bit = pin & pctl->devdata->mode_mask; + reg_pullen = mtk_get_port(pctl, pin) + + pctl->devdata->pullen_offset; + reg_pullsel = mtk_get_port(pctl, pin) + + pctl->devdata->pullsel_offset; + + regmap_update_bits(mtk_get_regmap(pctl, pin), reg_pullen, + BIT(bit), enable << bit); + regmap_update_bits(mtk_get_regmap(pctl, pin), reg_pullsel, + BIT(bit), isup << bit); + } else { + bit = BIT(pin & pctl->devdata->mode_mask); + if (enable) + reg_pullen = SET_ADDR(mtk_get_port(pctl, pin) + + pctl->devdata->pullen_offset, pctl); + else + reg_pullen = CLR_ADDR(mtk_get_port(pctl, pin) + + pctl->devdata->pullen_offset, pctl); + + if (isup) + reg_pullsel = SET_ADDR(mtk_get_port(pctl, pin) + + pctl->devdata->pullsel_offset, pctl); + else + reg_pullsel = CLR_ADDR(mtk_get_port(pctl, pin) + + pctl->devdata->pullsel_offset, pctl); + + regmap_write(mtk_get_regmap(pctl, pin), reg_pullen, bit); + regmap_write(mtk_get_regmap(pctl, pin), reg_pullsel, bit); + } - regmap_write(mtk_get_regmap(pctl, pin), reg_pullen, bit); - regmap_write(mtk_get_regmap(pctl, pin), reg_pullsel, bit); return 0; } diff --git a/drivers/pinctrl/mediatek/pinctrl-mtk-common.h b/drivers/pinctrl/mediatek/pinctrl-mtk-common.h index 6fe8564334c9..cc0dce8818c6 100644 --- a/drivers/pinctrl/mediatek/pinctrl-mtk-common.h +++ b/drivers/pinctrl/mediatek/pinctrl-mtk-common.h @@ -22,6 +22,8 @@ #define MTK_PINCTRL_NOT_SUPPORT (0xffff) +#define MTK_PINCTRL_MODE_SET_CLR_BROKEN BIT(0) + struct mtk_desc_function { const char *name; unsigned char muxval; @@ -271,6 +273,7 @@ struct mtk_pinctrl_devdata { unsigned int mode_mask; unsigned int mode_per_reg; unsigned int mode_shf; + unsigned long quirks; }; struct mtk_pinctrl {