diff mbox series

[2/2] pinctrl: mediatek: mt8365: use MTK_PINCTRL_MODE_SET_CLR_BROKEN quirk

Message ID 20220530123425.689459-2-fparent@baylibre.com (mailing list archive)
State New, archived
Headers show
Series [1/2] pinctrl: mediatek: common: add quirk for broken set/clr modes | expand

Commit Message

Fabien Parent May 30, 2022, 12:34 p.m. UTC 
On MT8365, the GPIO64 modes cannot be set using the SET/CLR register.
Use the MTK_PINCTRL_MODE_SET_CLR_BROKEN quirk to workaround it.

Signed-off-by: Fabien Parent <fparent@baylibre.com>
---
 drivers/pinctrl/mediatek/pinctrl-mt8365.c | 1 +
 1 file changed, 1 insertion(+)
diff mbox series

Patch

diff --git a/drivers/pinctrl/mediatek/pinctrl-mt8365.c b/drivers/pinctrl/mediatek/pinctrl-mt8365.c
index 57f37a294063..a49fa685f5f5 100644
--- a/drivers/pinctrl/mediatek/pinctrl-mt8365.c
+++ b/drivers/pinctrl/mediatek/pinctrl-mt8365.c
@@ -454,6 +454,7 @@  static const struct mtk_pinctrl_devdata mt8365_pinctrl_data = {
 		.ap_num = 160,
 		.db_cnt = 160,
 	},
+	.quirks = MTK_PINCTRL_MODE_SET_CLR_BROKEN,
 };
 
 static const struct of_device_id mt8365_pctrl_match[] = {