From patchwork Mon May 30 20:42:14 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Fabien Parent X-Patchwork-Id: 12864948 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 30733C433EF for ; Mon, 30 May 2022 20:44:27 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=OHj8dJY7tNWn8nmpYotppRnUWSaHe3AokCs886dFinE=; b=4Czi+lpHUmWZUq UWkx9NOZc2APzy6teGY1+kEs0uVgi7i5Hcq+npNo6BgGBo1/+NHAXM+/0xODmV64fHQVc7V0d/WRp 9hX6WP/WOSpWj0F4q+gS7KPPUbuGWGm51MejLNinl6oZowaibZlT1AvCp1YbQ35lSQ0kW410UtzMr g7C1po80HVzPIZeTsugUyv8fBWWWj+5CKfH1kvTsn6NhHR0a8J4PrkPAYDO6g6tZXsjTHltC7Upf1 MpI0RcolTvko/zXBOsQLx9A3xCdfjI3mpjLAply9PH5pZGTuBSB7x9PjG0aNemygSezteNWeUxS1a QVc1SipdZSbHvrQBojJA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1nvmEJ-008FG0-Rg; Mon, 30 May 2022 20:43:11 +0000 Received: from mail-wm1-x32d.google.com ([2a00:1450:4864:20::32d]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1nvmDk-008Exf-QF for linux-arm-kernel@lists.infradead.org; Mon, 30 May 2022 20:42:38 +0000 Received: by mail-wm1-x32d.google.com with SMTP id f23-20020a7bcc17000000b003972dda143eso158803wmh.3 for ; Mon, 30 May 2022 13:42:34 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20210112.gappssmtp.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=g1BTI86GlCK1B9gqDk4gnt+V9Nf1fSdYsJY6Md6XtoU=; b=kY99WDkAWVOh54SCO/3qB4XP6Gi7HB9yfTH90kF7z+qu2VBkXD8+vTIhquydAl1JJE RavN3eE5RXzZBrGuXEbiB6wDAgPVOexZTp9tgURhT4bQ1corzFDmtxnt2tHegysUWRuA FQxLUHvA6FXqUSZdyohgSRnjqINZ4y2BuGlKJASGCLh9gsXyIMA3QYueow5H18XiNhp+ pfHiWxrcxx/Uzwsa5evosRMKlZXWudITswFqMKxFdvGoyjEqQyaqaWKXJhJhgbUnYz4g bonRn6KqU2YHi8Y4XUryATwDdwv74NFCoegeLKQcu9h9ZeSgFkdmmIGQuFTLyZfVwqqf K9tg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=g1BTI86GlCK1B9gqDk4gnt+V9Nf1fSdYsJY6Md6XtoU=; b=agc5Ts2CWOA9OljgpS0y0H/O0IocZfnM5tMGCd+1k+B0hTgGOZdBL17N8Dvp/eY4Ph kWVTnuYehqEXPA5HkDkunNPpM5HS8SfuKwwuq23P0oVzIheb9zbILrKxNqIgQDNDjymZ IOFcjrRQ2z8F2Tiuh5FY8vfN9zrMwR9S8yAdubOnWY24c+CIP+ddD3+1XUl0geh3ZjEk 8YBkeq60cIiSsysiddD/A8ToBwqA4oxCSRMh4xlZiaS+D8BHwFScku7tZw9+ODWYfuua C0tVWFg3MwGc2Vll1cKG7Z5ktzeeImp0PfN8BP4RqEcFhqrguk6qsw+eC9d1NMoMu27D vl5g== X-Gm-Message-State: AOAM53146peERbbFAcLscUgxupQkPacMmWUmzw1E/XrrK+B1sN7EL9G2 5snlvIimINQISHqY687k5LvlWA== X-Google-Smtp-Source: ABdhPJztwgk5E+JDeFhXu/KM8ELV1Vby7n3FQo7UPBdmqMRL6mBAbLlk2+XaDJR2ujnjhdfdgWG5jA== X-Received: by 2002:a05:600c:4f4d:b0:394:6ead:3523 with SMTP id m13-20020a05600c4f4d00b003946ead3523mr20392821wmq.109.1653943353248; Mon, 30 May 2022 13:42:33 -0700 (PDT) Received: from localhost.localdomain ([88.160.162.107]) by smtp.gmail.com with ESMTPSA id w13-20020a7bc74d000000b0039b17714eb2sm262253wmk.34.2022.05.30.13.42.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 30 May 2022 13:42:32 -0700 (PDT) From: Fabien Parent To: Matthias Brugger Cc: Fabien Parent , linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org Subject: [PATCH 4/4] soc: mediatek: pm-domains: Add support for MT8365 Date: Mon, 30 May 2022 22:42:14 +0200 Message-Id: <20220530204214.913251-4-fparent@baylibre.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20220530204214.913251-1-fparent@baylibre.com> References: <20220530204214.913251-1-fparent@baylibre.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220530_134236_960986_770D74C4 X-CRM114-Status: GOOD ( 18.01 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Add the needed board data to support MT8365 SoC. Signed-off-by: Fabien Parent --- drivers/soc/mediatek/mt8365-pm-domains.h | 147 +++++++++++++++++++++++ drivers/soc/mediatek/mtk-pm-domains.c | 5 + 2 files changed, 152 insertions(+) create mode 100644 drivers/soc/mediatek/mt8365-pm-domains.h diff --git a/drivers/soc/mediatek/mt8365-pm-domains.h b/drivers/soc/mediatek/mt8365-pm-domains.h new file mode 100644 index 000000000000..d5097d0741f7 --- /dev/null +++ b/drivers/soc/mediatek/mt8365-pm-domains.h @@ -0,0 +1,147 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __SOC_MEDIATEK_MT8365_PM_DOMAINS_H +#define __SOC_MEDIATEK_MT8365_PM_DOMAINS_H + +#include "mtk-pm-domains.h" +#include + +/* + * MT8365 power domain support + */ + +static const struct scpsys_domain_data scpsys_domain_data_mt8365[] = { + [MT8365_POWER_DOMAIN_MM] = { + .name = "mm", + .sta_mask = PWR_STATUS_DISP, + .ctl_offs = 0x30c, + .pwr_sta_offs = 0x0180, + .pwr_sta2nd_offs = 0x0184, + .sram_pdn_bits = GENMASK(8, 8), + .sram_pdn_ack_bits = GENMASK(12, 12), + .caps = MTK_SCPD_STRICT_BUSP, + .bp_infracfg = { + BUS_PROT_WR(BIT(16) | BIT(17), 0x2a8, 0x2ac, 0x258), + BUS_PROT_WR(BIT(1) | BIT(2) | BIT(10) | BIT(11), 0x2a0, 0x2a4, 0x228), + BUS_PROT_WAYEN(BIT(6), BIT(24), 0x200, 0x0), + BUS_PROT_WAYEN(BIT(5), BIT(14), 0x234, 0x28), + BUS_PROT_WR(BIT(6), 0x2a0, 0x2a4, 0x228), + }, + }, + [MT8365_POWER_DOMAIN_VENC] = { + .name = "venc", + .sta_mask = PWR_STATUS_VENC, + .ctl_offs = 0x0304, + .pwr_sta_offs = 0x0180, + .pwr_sta2nd_offs = 0x0184, + .sram_pdn_bits = GENMASK(8, 8), + .sram_pdn_ack_bits = GENMASK(12, 12), + .bp_smi = { + BUS_PROT_WR(BIT(1), 0x3c4, 0x3c8, 0x3c0), + }, + }, + [MT8365_POWER_DOMAIN_AUDIO] = { + .name = "audio", + .sta_mask = PWR_STATUS_AUDIO, + .ctl_offs = 0x0314, + .pwr_sta_offs = 0x0180, + .pwr_sta2nd_offs = 0x0184, + .sram_pdn_bits = GENMASK(12, 8), + .sram_pdn_ack_bits = GENMASK(17, 13), + .bp_infracfg = { + BUS_PROT_WR(BIT(27) | BIT(28), 0x2a8, 0x2ac, 0x258), + }, + .caps = MTK_SCPD_ACTIVE_WAKEUP, + }, + [MT8365_POWER_DOMAIN_CONN] = { + .name = "conn", + .sta_mask = PWR_STATUS_CONN, + .ctl_offs = 0x032c, + .pwr_sta_offs = 0x0180, + .pwr_sta2nd_offs = 0x0184, + .sram_pdn_bits = 0, + .sram_pdn_ack_bits = 0, + .bp_infracfg = { + BUS_PROT_WR(BIT(13), 0x2a0, 0x2a4, 0x228), + BUS_PROT_WR(BIT(18), 0x2a8, 0x2ac, 0x258), + BUS_PROT_WR(BIT(14), 0x2a0, 0x2a4, 0x228), + BUS_PROT_WR(BIT(21), 0x2a8, 0x2ac, 0x258), + }, + .caps = MTK_SCPD_ACTIVE_WAKEUP | MTK_SCPD_KEEP_DEFAULT_OFF, + }, + [MT8365_POWER_DOMAIN_MFG] = { + .name = "mfg", + .sta_mask = PWR_STATUS_MFG, + .ctl_offs = 0x0338, + .pwr_sta_offs = 0x0180, + .pwr_sta2nd_offs = 0x0184, + .sram_pdn_bits = GENMASK(9, 8), + .sram_pdn_ack_bits = GENMASK(13, 12), + .bp_infracfg = { + BUS_PROT_WR(BIT(25), 0x2a0, 0x2a4, 0x228), + BUS_PROT_WR(BIT(21) | BIT(22), 0x2a0, 0x2a4, 0x228), + }, + }, + [MT8365_POWER_DOMAIN_CAM] = { + .name = "cam", + .sta_mask = BIT(25), + .ctl_offs = 0x0344, + .pwr_sta_offs = 0x0180, + .pwr_sta2nd_offs = 0x0184, + .sram_pdn_bits = GENMASK(9, 8), + .sram_pdn_ack_bits = GENMASK(13, 12), + .bp_infracfg = { + BUS_PROT_WR(BIT(19), 0x2a8, 0x2ac, 0x258), + }, + .bp_smi = { + BUS_PROT_WR(BIT(2), 0x3c4, 0x3c8, 0x3c0), + }, + }, + [MT8365_POWER_DOMAIN_VDEC] = { + .name = "vdec", + .sta_mask = BIT(31), + .ctl_offs = 0x0370, + .pwr_sta_offs = 0x0180, + .pwr_sta2nd_offs = 0x0184, + .sram_pdn_bits = GENMASK(8, 8), + .sram_pdn_ack_bits = GENMASK(12, 12), + .bp_smi = { + BUS_PROT_WR(BIT(3), 0x3c4, 0x3c8, 0x3c0), + }, + }, + [MT8365_POWER_DOMAIN_APU] = { + .name = "apu", + .sta_mask = BIT(16), + .ctl_offs = 0x0378, + .pwr_sta_offs = 0x0180, + .pwr_sta2nd_offs = 0x0184, + .sram_pdn_bits = GENMASK(14, 8), + .sram_pdn_ack_bits = GENMASK(21, 15), + .bp_infracfg = { + BUS_PROT_WR(BIT(2) | BIT(20), 0x2a8, 0x2ac, 0x258), + }, + .bp_smi = { + BUS_PROT_WR(BIT(4), 0x3c4, 0x3c8, 0x3c0), + }, + }, + [MT8365_POWER_DOMAIN_DSP] = { + .name = "dsp", + .sta_mask = BIT(17), + .ctl_offs = 0x037C, + .pwr_sta_offs = 0x0180, + .pwr_sta2nd_offs = 0x0184, + .sram_pdn_bits = GENMASK(11, 8), + .sram_pdn_ack_bits = GENMASK(15, 12), + .bp_infracfg = { + BUS_PROT_WR(BIT(24) | BIT(30) | BIT(31), 0x2a8, 0x2ac, 0x258), + }, + .caps = MTK_SCPD_ACTIVE_WAKEUP, + }, +}; + +static const struct scpsys_soc_data mt8365_scpsys_data = { + .domains_data = scpsys_domain_data_mt8365, + .num_domains = ARRAY_SIZE(scpsys_domain_data_mt8365), +}; + +#endif /* __SOC_MEDIATEK_MT8365_PM_DOMAINS_H */ diff --git a/drivers/soc/mediatek/mtk-pm-domains.c b/drivers/soc/mediatek/mtk-pm-domains.c index beaa5785fda2..1f922db7eddf 100644 --- a/drivers/soc/mediatek/mtk-pm-domains.c +++ b/drivers/soc/mediatek/mtk-pm-domains.c @@ -22,6 +22,7 @@ #include "mt8186-pm-domains.h" #include "mt8192-pm-domains.h" #include "mt8195-pm-domains.h" +#include "mt8365-pm-domains.h" #define MTK_POLL_DELAY_US 10 #define MTK_POLL_TIMEOUT USEC_PER_SEC @@ -634,6 +635,10 @@ static const struct of_device_id scpsys_of_match[] = { .compatible = "mediatek,mt8195-power-controller", .data = &mt8195_scpsys_data, }, + { + .compatible = "mediatek,mt8365-power-controller", + .data = &mt8365_scpsys_data, + }, { } };