| Message ID | 20220531121913.48722-4-chanho61.park@samsung.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | support secondary ufs for Exynos Auto v9 SoC | expand |
On 31/05/2022 14:19, Chanho Park wrote: > Add ufs_1_phy and ufs_1 for secondary ufs hci controller and phy > device. > > Signed-off-by: Chanho Park <chanho61.park@samsung.com> > --- > arch/arm64/boot/dts/exynos/exynosautov9.dtsi | 32 ++++++++++++++++++++ > 1 file changed, 32 insertions(+) > > diff --git a/arch/arm64/boot/dts/exynos/exynosautov9.dtsi b/arch/arm64/boot/dts/exynos/exynosautov9.dtsi > index 3e23db8f09d9..c146271af477 100644 > --- a/arch/arm64/boot/dts/exynos/exynosautov9.dtsi > +++ b/arch/arm64/boot/dts/exynos/exynosautov9.dtsi > @@ -380,6 +380,17 @@ ufs_0_phy: ufs0-phy@17e04000 { > status = "disabled"; > }; > > + ufs_1_phy: ufs0-phy@17f04000 { Node name: "phy" (or ufs-phy). The previous node also could be corrected. > + compatible = "samsung,exynosautov9-ufs-phy"; > + reg = <0x17f04000 0xc00>; > + reg-names = "phy-pma"; > + samsung,pmu-syscon = <&pmu_system_controller 0x72c>; > + #phy-cells = <0>; > + clocks = <&xtcxo>; > + clock-names = "ref_clk"; > + status = "disabled"; > + }; > + > ufs_0: ufs0@17e00000 { > compatible ="samsung,exynosautov9-ufs"; > > @@ -400,6 +411,27 @@ ufs_0: ufs0@17e00000 { > samsung,sysreg = <&syscon_fsys2 0x710>; > status = "disabled"; > }; > + > + ufs_1: ufs0@17f00000 { > + compatible ="samsung,exynosautov9-ufs"; > + > + reg = <0x17f00000 0x100>, /* 0: HCI standard */ > + <0x17f01100 0x410>, /* 1: Vendor-specific */ > + <0x17f80000 0x8000>, /* 2: UNIPRO */ > + <0x17de0000 0x2200>; /* 3: UFS protector */ Align these please with first <> entry. > + reg-names = "hci", "vs_hci", "unipro", "ufsp"; > + interrupts = <GIC_SPI 235 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&cmu_fsys2 CLK_GOUT_FSYS2_UFS_EMBD1_ACLK>, > + <&cmu_fsys2 CLK_GOUT_FSYS2_UFS_EMBD1_UNIPRO>; > + clock-names = "core_clk", "sclk_unipro_main"; > + freq-table-hz = <0 0>, <0 0>; > + pinctrl-names = "default"; > + pinctrl-0 = <&ufs_rst_n_1 &ufs_refclk_out_1>; > + phys = <&ufs_1_phy>; > + phy-names = "ufs-phy"; > + samsung,sysreg = <&syscon_fsys2 0x714>; > + status = "disabled"; > + }; > }; > }; > Best regards, Krzysztof
> > + ufs_1_phy: ufs0-phy@17f04000 { > > Node name: "phy" (or ufs-phy). The previous node also could be corrected. phy@17f04000 looks better. I'll change this and make an additional patch to correct previous ufs0 nodes. > > > + compatible = "samsung,exynosautov9-ufs-phy"; > > + reg = <0x17f04000 0xc00>; > > + reg-names = "phy-pma"; > > + samsung,pmu-syscon = <&pmu_system_controller 0x72c>; > > + #phy-cells = <0>; > > + clocks = <&xtcxo>; > > + clock-names = "ref_clk"; > > + status = "disabled"; > > + }; > > + > > ufs_0: ufs0@17e00000 { > > compatible ="samsung,exynosautov9-ufs"; > > > > @@ -400,6 +411,27 @@ ufs_0: ufs0@17e00000 { > > samsung,sysreg = <&syscon_fsys2 0x710>; > > status = "disabled"; > > }; > > + > > + ufs_1: ufs0@17f00000 { > > + compatible ="samsung,exynosautov9-ufs"; > > + > > + reg = <0x17f00000 0x100>, /* 0: HCI standard */ > > + <0x17f01100 0x410>, /* 1: Vendor-specific */ > > + <0x17f80000 0x8000>, /* 2: UNIPRO */ > > + <0x17de0000 0x2200>; /* 3: UFS protector */ > > Align these please with first <> entry. I'll apply this on the next patchset and fix the same on ufs0 node as well. Best Regards, Chanho Park
diff --git a/arch/arm64/boot/dts/exynos/exynosautov9.dtsi b/arch/arm64/boot/dts/exynos/exynosautov9.dtsi index 3e23db8f09d9..c146271af477 100644 --- a/arch/arm64/boot/dts/exynos/exynosautov9.dtsi +++ b/arch/arm64/boot/dts/exynos/exynosautov9.dtsi @@ -380,6 +380,17 @@ ufs_0_phy: ufs0-phy@17e04000 { status = "disabled"; }; + ufs_1_phy: ufs0-phy@17f04000 { + compatible = "samsung,exynosautov9-ufs-phy"; + reg = <0x17f04000 0xc00>; + reg-names = "phy-pma"; + samsung,pmu-syscon = <&pmu_system_controller 0x72c>; + #phy-cells = <0>; + clocks = <&xtcxo>; + clock-names = "ref_clk"; + status = "disabled"; + }; + ufs_0: ufs0@17e00000 { compatible ="samsung,exynosautov9-ufs"; @@ -400,6 +411,27 @@ ufs_0: ufs0@17e00000 { samsung,sysreg = <&syscon_fsys2 0x710>; status = "disabled"; }; + + ufs_1: ufs0@17f00000 { + compatible ="samsung,exynosautov9-ufs"; + + reg = <0x17f00000 0x100>, /* 0: HCI standard */ + <0x17f01100 0x410>, /* 1: Vendor-specific */ + <0x17f80000 0x8000>, /* 2: UNIPRO */ + <0x17de0000 0x2200>; /* 3: UFS protector */ + reg-names = "hci", "vs_hci", "unipro", "ufsp"; + interrupts = <GIC_SPI 235 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cmu_fsys2 CLK_GOUT_FSYS2_UFS_EMBD1_ACLK>, + <&cmu_fsys2 CLK_GOUT_FSYS2_UFS_EMBD1_UNIPRO>; + clock-names = "core_clk", "sclk_unipro_main"; + freq-table-hz = <0 0>, <0 0>; + pinctrl-names = "default"; + pinctrl-0 = <&ufs_rst_n_1 &ufs_refclk_out_1>; + phys = <&ufs_1_phy>; + phy-names = "ufs-phy"; + samsung,sysreg = <&syscon_fsys2 0x714>; + status = "disabled"; + }; }; };
Add ufs_1_phy and ufs_1 for secondary ufs hci controller and phy device. Signed-off-by: Chanho Park <chanho61.park@samsung.com> --- arch/arm64/boot/dts/exynos/exynosautov9.dtsi | 32 ++++++++++++++++++++ 1 file changed, 32 insertions(+)