| Message ID | 20220601004244.27394-3-william.zhang@broadcom.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | arm64: bcmbca: add bcm4912 SoC support | expand |
On 5/31/2022 5:42 PM, William Zhang wrote: > Add dts for ARMv8 based broadband SoC BCM4912. bcm4912.dtsi is the > SoC description dts header and bcm94912.dts is a simple dts file for > Broadcom BCM94912 Reference board that only enable the UART port. > > Signed-off-by: William Zhang <william.zhang@broadcom.com> > > --- [snip] > + > + axi@81000000 { > + compatible = "simple-bus"; > + #address-cells = <2>; > + #size-cells = <2>; See comment below for the ubus node. > + ranges = <0x0 0x0 0x0 0x81000000 0x0 0x8000>; > + > + gic: interrupt-controller@1000 { > + compatible = "arm,gic-400"; > + #interrupt-cells = <3>; > + interrupt-controller; > + interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; > + reg = <0x0 0x1000 0x0 0x1000>, > + <0x0 0x2000 0x0 0x2000>, > + <0x0 0x4000 0x0 0x2000>, > + <0x0 0x6000 0x0 0x2000>; > + }; > + }; > + > + bus@ff800000 { > + compatible = "simple-bus"; > + #address-cells = <2>; > + #size-cells = <2>; This does not quite make sense, as I doubt that this part of the bus is 64-bit capable, rather, I would expect to find both #address-cells and #size-cells to be set to 1 and ... (see below) > + ranges = <0x0 0x0 0x0 0xff800000 0x0 0x800000>; > + > + uart0: serial@12000 { > + compatible = "arm,pl011", "arm,primecell"; > + reg = <0x0 0x12000 0x0 0x1000>; ... have this become simply: reg = <0x12000 0x1000>: which also looks awfully big for an UART block, an entire 4KB worth of register space?
On 6/1/22 02:47, Florian Fainelli wrote: > > > On 5/31/2022 5:42 PM, William Zhang wrote: >> Add dts for ARMv8 based broadband SoC BCM4912. bcm4912.dtsi is the >> SoC description dts header and bcm94912.dts is a simple dts file for >> Broadcom BCM94912 Reference board that only enable the UART port. >> >> Signed-off-by: William Zhang <william.zhang@broadcom.com> >> >> --- > > [snip] > >> + >> + axi@81000000 { >> + compatible = "simple-bus"; >> + #address-cells = <2>; >> + #size-cells = <2>; > > See comment below for the ubus node. > >> + ranges = <0x0 0x0 0x0 0x81000000 0x0 0x8000>; >> + >> + gic: interrupt-controller@1000 { >> + compatible = "arm,gic-400"; >> + #interrupt-cells = <3>; >> + interrupt-controller; >> + interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | >> IRQ_TYPE_LEVEL_HIGH)>; >> + reg = <0x0 0x1000 0x0 0x1000>, >> + <0x0 0x2000 0x0 0x2000>, >> + <0x0 0x4000 0x0 0x2000>, >> + <0x0 0x6000 0x0 0x2000>; >> + }; >> + }; >> + >> + bus@ff800000 { >> + compatible = "simple-bus"; >> + #address-cells = <2>; >> + #size-cells = <2>; > > This does not quite make sense, as I doubt that this part of the bus is > 64-bit capable, rather, I would expect to find both #address-cells and > #size-cells to be set to 1 and ... (see below) > Agree. It can be simplified to use 32 bit address and size. >> + ranges = <0x0 0x0 0x0 0xff800000 0x0 0x800000>; >> + >> + uart0: serial@12000 { >> + compatible = "arm,pl011", "arm,primecell"; >> + reg = <0x0 0x12000 0x0 0x1000>; > > ... have this become simply: > > reg = <0x12000 0x1000>: > > which also looks awfully big for an UART block, an entire 4KB worth of > register space? That is the correct based on the rdb.
diff --git a/arch/arm64/boot/dts/broadcom/bcmbca/Makefile b/arch/arm64/boot/dts/broadcom/bcmbca/Makefile index d5f89245336c..9bdab7778cbd 100644 --- a/arch/arm64/boot/dts/broadcom/bcmbca/Makefile +++ b/arch/arm64/boot/dts/broadcom/bcmbca/Makefile @@ -1,2 +1,3 @@ # SPDX-License-Identifier: GPL-2.0 -dtb-$(CONFIG_ARCH_BCMBCA) += bcm963158.dtb +dtb-$(CONFIG_ARCH_BCMBCA) += bcm963158.dtb \ + bcm94912.dtb diff --git a/arch/arm64/boot/dts/broadcom/bcmbca/bcm4912.dtsi b/arch/arm64/boot/dts/broadcom/bcmbca/bcm4912.dtsi new file mode 100644 index 000000000000..25dbc19731f0 --- /dev/null +++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm4912.dtsi @@ -0,0 +1,128 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2022 Broadcom Ltd. + */ + +#include <dt-bindings/interrupt-controller/irq.h> +#include <dt-bindings/interrupt-controller/arm-gic.h> + +/ { + compatible = "brcm,bcm4912", "brcm,bcmbca"; + #address-cells = <2>; + #size-cells = <2>; + + interrupt-parent = <&gic>; + + cpus { + #address-cells = <2>; + #size-cells = <0>; + + B53_0: cpu@0 { + compatible = "brcm,brahma-b53"; + device_type = "cpu"; + reg = <0x0 0x0>; + next-level-cache = <&L2_0>; + enable-method = "psci"; + }; + + B53_1: cpu@1 { + compatible = "brcm,brahma-b53"; + device_type = "cpu"; + reg = <0x0 0x1>; + next-level-cache = <&L2_0>; + enable-method = "psci"; + }; + + B53_2: cpu@2 { + compatible = "brcm,brahma-b53"; + device_type = "cpu"; + reg = <0x0 0x2>; + next-level-cache = <&L2_0>; + enable-method = "psci"; + }; + + B53_3: cpu@3 { + compatible = "brcm,brahma-b53"; + device_type = "cpu"; + reg = <0x0 0x3>; + next-level-cache = <&L2_0>; + enable-method = "psci"; + }; + + L2_0: l2-cache0 { + compatible = "cache"; + }; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; + }; + + pmu: pmu { + compatible = "arm,cortex-a53-pmu"; + interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; + interrupt-affinity = <&B53_0>, <&B53_1>, + <&B53_2>, <&B53_3>; + }; + + clocks: clocks { + periph_clk: periph-clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <200000000>; + }; + uart_clk: uart-clk { + compatible = "fixed-factor-clock"; + #clock-cells = <0>; + clocks = <&periph_clk>; + clock-div = <4>; + clock-mult = <1>; + }; + }; + + psci { + compatible = "arm,psci-0.2"; + method = "smc"; + }; + + axi@81000000 { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + ranges = <0x0 0x0 0x0 0x81000000 0x0 0x8000>; + + gic: interrupt-controller@1000 { + compatible = "arm,gic-400"; + #interrupt-cells = <3>; + interrupt-controller; + interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; + reg = <0x0 0x1000 0x0 0x1000>, + <0x0 0x2000 0x0 0x2000>, + <0x0 0x4000 0x0 0x2000>, + <0x0 0x6000 0x0 0x2000>; + }; + }; + + bus@ff800000 { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + ranges = <0x0 0x0 0x0 0xff800000 0x0 0x800000>; + + uart0: serial@12000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x0 0x12000 0x0 0x1000>; + interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&uart_clk>, <&uart_clk>; + clock-names = "uartclk", "apb_pclk"; + status = "disabled"; + }; + }; +}; diff --git a/arch/arm64/boot/dts/broadcom/bcmbca/bcm94912.dts b/arch/arm64/boot/dts/broadcom/bcmbca/bcm94912.dts new file mode 100644 index 000000000000..a3623e6f6919 --- /dev/null +++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm94912.dts @@ -0,0 +1,30 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2022 Broadcom Ltd. + */ + +/dts-v1/; + +#include "bcm4912.dtsi" + +/ { + model = "Broadcom BCM94912 Reference Board"; + compatible = "brcm,bcm94912", "brcm,bcm4912", "brcm,bcmbca"; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x0 0x0 0x08000000>; + }; +}; + +&uart0 { + status = "okay"; +};
Add dts for ARMv8 based broadband SoC BCM4912. bcm4912.dtsi is the SoC description dts header and bcm94912.dts is a simple dts file for Broadcom BCM94912 Reference board that only enable the UART port. Signed-off-by: William Zhang <william.zhang@broadcom.com> --- Changes in v2: - Fix pmu compatible string - Remove unnecessary cpu_on and cpu_off properties from psci node - Add the missing gic registers and interrupts property to gic node arch/arm64/boot/dts/broadcom/bcmbca/Makefile | 3 +- .../boot/dts/broadcom/bcmbca/bcm4912.dtsi | 128 ++++++++++++++++++ .../boot/dts/broadcom/bcmbca/bcm94912.dts | 30 ++++ 3 files changed, 160 insertions(+), 1 deletion(-) create mode 100644 arch/arm64/boot/dts/broadcom/bcmbca/bcm4912.dtsi create mode 100644 arch/arm64/boot/dts/broadcom/bcmbca/bcm94912.dts