Message ID | 20220606064935.1458903-4-neal_liu@aspeedtech.com (mailing list archive) |
---|---|
State | New, archived |
Headers | show |
Series | Add Aspeed crypto driver for hardware acceleration | expand |
On 6/5/2022 11:49 PM, Neal Liu wrote: > diff --git a/arch/arm/boot/dts/aspeed-g6.dtsi b/arch/arm/boot/dts/aspeed-g6.dtsi > index 3d5ce9da42c3..371d2a6b56ef 100644 > --- a/arch/arm/boot/dts/aspeed-g6.dtsi > +++ b/arch/arm/boot/dts/aspeed-g6.dtsi > @@ -304,6 +304,14 @@ apb { > #size-cells = <1>; > ranges; > > + hace: crypto@1e6d0000 { > + compatible = "aspeed,ast2600-hace"; > + reg = <0x1e6d0000 0x200>; > + interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&syscon ASPEED_CLK_GATE_YCLK>; > + resets = <&syscon ASPEED_RESET_HACE>; Shouldn't the left side be also 'crypto', see existing crypto nodes in arch/arm64/dts for example. crypto: crypto@1e6d0000 { ... Regards, Dhananjay
diff --git a/arch/arm/boot/dts/aspeed-g6.dtsi b/arch/arm/boot/dts/aspeed-g6.dtsi index 3d5ce9da42c3..371d2a6b56ef 100644 --- a/arch/arm/boot/dts/aspeed-g6.dtsi +++ b/arch/arm/boot/dts/aspeed-g6.dtsi @@ -304,6 +304,14 @@ apb { #size-cells = <1>; ranges; + hace: crypto@1e6d0000 { + compatible = "aspeed,ast2600-hace"; + reg = <0x1e6d0000 0x200>; + interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&syscon ASPEED_CLK_GATE_YCLK>; + resets = <&syscon ASPEED_RESET_HACE>; + }; + syscon: syscon@1e6e2000 { compatible = "aspeed,ast2600-scu", "syscon", "simple-mfd"; reg = <0x1e6e2000 0x1000>;