From patchwork Mon Jun 6 14:57:01 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?Q2zDqW1lbnQgTMOpZ2Vy?= X-Patchwork-Id: 12870485 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 95AA5C43334 for ; Mon, 6 Jun 2022 14:59:53 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=69/hIJAadro8L9WFTmfFEBmTEoKRBToptd4Ba+A10cs=; b=v2T5aOFpUx+1x1 XLhRm5QhvZDIbOL9NkZx2f+qQm8uOXgTtuM7P3Fs3C04lT/wGqjWJlbrVd7wq4lwRVsXtC3tBM6pH EfXsOU2rSAWVAXgb8Jgn6WOhqMbrNweddNrZz4jr4D9IcdT3CbdnekW8f1H8KhzhORDgU8VbPC6Ts dDqaeAazn5R7LlMh555xBWSoA5iNjlb3Fzx3NCJ3gbtDvfzABBZBWd9/Y/TKEe6SKAShCnIMlq3qj pHpAk8BJLOCUa9lnSLyltJL2u1aT8vXk0TIbgMwo3GC+Q6yYW/VHbSWwyj7WSZ3kdcKOysXcPWD+l BtlJLPFEnsjSvNAoDEmA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1nyEBj-001d86-Tx; Mon, 06 Jun 2022 14:58:40 +0000 Received: from relay9-d.mail.gandi.net ([217.70.183.199]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1nyEBR-001czL-1Q for linux-arm-kernel@lists.infradead.org; Mon, 06 Jun 2022 14:58:22 +0000 Received: (Authenticated sender: clement.leger@bootlin.com) by mail.gandi.net (Postfix) with ESMTPSA id D8D91FF808; Mon, 6 Jun 2022 14:58:15 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=gm1; t=1654527496; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=SMDzIUH01c9Xmou891SUin6Y2SHspdo6jDEEnRQIDZg=; b=BhZLT0bNjLOlGCma7K7u9yCrwmEdw+TSDMwUUXqotxtjL2P+p1/MVVB9D1jDWuLOn2iyT0 gP1xiXcT/gw6lYTUDScsWG2WkRk8nkFmQfqiWBQnLuPTV/s+8Xdvv59A9CqFXT3TO5Z59o qk7SEqx+On9gOSAzKwIFmYy27GLwxLPfaGRu/OOM1UsTdnXjjmarbbRMfgpxPao6F5/rvS 3AcH2+ZpEH/k/m1G+o+rUe2I7MMlFspjTTAtzFw99PbZUQmTRSTsNW/liLVDMIbe4eLsNA SvqRX1NE3ZExU2v6lRR3vKZxyuSVOrHGdwAfqO9taenTtS9xCs4N0jEDoFxLGw== From: =?utf-8?b?Q2zDqW1lbnQgTMOpZ2Vy?= To: Russell King , Nicolas Ferre , Alexandre Belloni , Claudiu Beznea Cc: =?utf-8?b?Q2zDqW1lbnQgTMOpZ2Vy?= , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Thomas Petazzoni Subject: [PATCH 2/2] ARM: at91: setup outer cache .write_sec() callback if needed Date: Mon, 6 Jun 2022 16:57:01 +0200 Message-Id: <20220606145701.185552-3-clement.leger@bootlin.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20220606145701.185552-1-clement.leger@bootlin.com> References: <20220606145701.185552-1-clement.leger@bootlin.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220606_075821_271132_BEB9F77E X-CRM114-Status: GOOD ( 12.49 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org When running under OP-TEE, the L2 cache is configured by OP-TEE and the sam platform code does not allow any modification yet. Setup a dummy .write_sec() callback to avoid triggering exceptions when Linux tries to modify the L2 cache configuration. Signed-off-by: Clément Léger --- arch/arm/mach-at91/sama5.c | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/arch/arm/mach-at91/sama5.c b/arch/arm/mach-at91/sama5.c index de5dd28b392e..d1a9e940a785 100644 --- a/arch/arm/mach-at91/sama5.c +++ b/arch/arm/mach-at91/sama5.c @@ -9,13 +9,27 @@ #include #include +#include #include #include +#include #include #include "generic.h" #include "sam_secure.h" +static void sama5_l2c310_write_sec(unsigned long val, unsigned reg) +{ + /* OP-TEE configures the L2 cache and does not allow modifying it yet */ +} + +static void __init sama5_secure_cache_init(void) +{ + sam_secure_init(); + if (sam_linux_is_in_normal_world()) + outer_cache.write_sec = sama5_l2c310_write_sec; +} + static void __init sama5_dt_device_init(void) { of_platform_default_populate(NULL, NULL, NULL); @@ -30,6 +44,7 @@ static const char *const sama5_dt_board_compat[] __initconst = { DT_MACHINE_START(sama5_dt, "Atmel SAMA5") /* Maintainer: Atmel */ .init_machine = sama5_dt_device_init, + .init_early = sama5_secure_cache_init, .dt_compat = sama5_dt_board_compat, MACHINE_END @@ -41,6 +56,7 @@ static const char *const sama5_alt_dt_board_compat[] __initconst = { DT_MACHINE_START(sama5_alt_dt, "Atmel SAMA5") /* Maintainer: Atmel */ .init_machine = sama5_dt_device_init, + .init_early = sama5_secure_cache_init, .dt_compat = sama5_alt_dt_board_compat, .l2c_aux_mask = ~0UL, MACHINE_END @@ -60,6 +76,7 @@ static const char *const sama5d2_compat[] __initconst = { DT_MACHINE_START(sama5d2, "Atmel SAMA5") /* Maintainer: Atmel */ .init_machine = sama5d2_init, + .init_early = sama5_secure_cache_init, .dt_compat = sama5d2_compat, .l2c_aux_mask = ~0UL, MACHINE_END