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Thu, 09 Jun 2022 17:21:57 -0700 (PDT) Received: from T3500-3.dhcp.broadcom.net ([192.19.223.252]) by smtp.gmail.com with ESMTPSA id lx9-20020a17090b4b0900b001e292e30129sm288877pjb.22.2022.06.09.17.21.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 09 Jun 2022 17:21:56 -0700 (PDT) From: William Zhang To: Linux ARM List Cc: dan.beygelman@broadcom.com, joel.peshkin@broadcom.com, samyon.furman@broadcom.com, philippe.reynes@softathome.com, Broadcom Kernel List , tomer.yacoby@broadcom.com, f.fainelli@gmail.com, kursad.oney@broadcom.com, anand.gore@broadcom.com, William Zhang , Arnd Bergmann , Krzysztof Kozlowski , Olof Johansson , Rob Herring , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, soc@kernel.org Subject: [PATCH 2/3] ARM: dts: Add DTS files for bcmbca SoC BCM63148 Date: Thu, 9 Jun 2022 17:21:12 -0700 Message-Id: <20220610002113.14483-3-william.zhang@broadcom.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20220610002113.14483-1-william.zhang@broadcom.com> References: <20220610002113.14483-1-william.zhang@broadcom.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220609_172201_115520_69288A01 X-CRM114-Status: GOOD ( 18.93 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Add DTS for ARMv7 based broadband SoC BCM63148. bcm63148.dtsi is the SoC description DTS header and bcm963148.dts is a simple DTS file for Broadcom BCM963148 Reference board that only enable the UART port. Signed-off-by: William Zhang --- arch/arm/boot/dts/Makefile | 1 + arch/arm/boot/dts/bcm63148.dtsi | 103 ++++++++++++++++++++++++++++++++ arch/arm/boot/dts/bcm963148.dts | 30 ++++++++++ 3 files changed, 134 insertions(+) create mode 100644 arch/arm/boot/dts/bcm63148.dtsi create mode 100644 arch/arm/boot/dts/bcm963148.dts diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 28af71650567..123cadcde448 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -183,6 +183,7 @@ dtb-$(CONFIG_ARCH_BRCMSTB) += \ bcm7445-bcm97445svmb.dtb dtb-$(CONFIG_ARCH_BCMBCA) += \ bcm947622.dtb \ + bcm963148.dtb \ bcm963178.dtb \ bcm96756.dtb \ bcm96846.dtb \ diff --git a/arch/arm/boot/dts/bcm63148.dtsi b/arch/arm/boot/dts/bcm63148.dtsi new file mode 100644 index 000000000000..df5307b6b3af --- /dev/null +++ b/arch/arm/boot/dts/bcm63148.dtsi @@ -0,0 +1,103 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2022 Broadcom Ltd. + */ + +#include +#include + +/ { + compatible = "brcm,bcm63148", "brcm,bcmbca"; + #address-cells = <1>; + #size-cells = <1>; + + interrupt-parent = <&gic>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + B15_0: cpu@0 { + device_type = "cpu"; + compatible = "brcm,brahma-b15"; + reg = <0x0>; + next-level-cache = <&L2_0>; + enable-method = "psci"; + }; + + B15_1: cpu@1 { + device_type = "cpu"; + compatible = "brcm,brahma-b15"; + reg = <0x1>; + next-level-cache = <&L2_0>; + enable-method = "psci"; + }; + + L2_0: l2-cache0 { + compatible = "cache"; + }; + }; + + timer { + compatible = "arm,armv7-timer"; + interrupts = , + , + , + ; + }; + + pmu: pmu { + compatible = "arm,cortex-a15-pmu"; + interrupts = , + ; + interrupt-affinity = <&B15_0>, <&B15_1>; + }; + + clocks: clocks { + periph_clk: periph-clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <50000000>; + }; + }; + + psci { + compatible = "arm,psci-0.2"; + method = "smc"; + }; + + axi@80030000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x80030000 0x8000>; + + gic: interrupt-controller@1000 { + compatible = "arm,cortex-a15-gic"; + #interrupt-cells = <3>; + interrupt-controller; + reg = <0x1000 0x1000>, + <0x2000 0x2000>, + <0x4000 0x2000>, + <0x6000 0x2000>; + interrupts = ; + }; + }; + + bus@ff800000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0xfffe8000 0x8000>; + + uart0: serial@600 { + compatible = "brcm,bcm6345-uart"; + reg = <0x600 0x20>; + interrupts = ; + clocks = <&periph_clk>; + clock-names = "refclk"; + status = "disabled"; + }; + }; +}; diff --git a/arch/arm/boot/dts/bcm963148.dts b/arch/arm/boot/dts/bcm963148.dts new file mode 100644 index 000000000000..98f6a6d09f50 --- /dev/null +++ b/arch/arm/boot/dts/bcm963148.dts @@ -0,0 +1,30 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2019 Broadcom Ltd. + */ + +/dts-v1/; + +#include "bcm63148.dtsi" + +/ { + model = "Broadcom BCM963148 Reference Board"; + compatible = "brcm,bcm963148", "brcm,bcm63148", "brcm,bcmbca"; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x08000000>; + }; +}; + +&uart0 { + status = "okay"; +};