From patchwork Wed Jun 15 23:15:44 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bjorn Helgaas X-Patchwork-Id: 12883037 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id EABA5C433EF for ; Wed, 15 Jun 2022 23:18:53 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=pSoy4kdoZJFIBYWL/whmm0lZYOFpC0OnnDppyoabKPk=; b=G6XKlnJ7P4yyxd 8NVEIfAGmeFNhKtVXipROwB/fM0RdnY2xA2o0DUfeIrLX79FxF8C0JwqfDQQZN/vEpI917lwFOuqv pzP3GRio7JuGx2SdcNUmRtDPvxY7W6LszbTrvpanX2NY4iDTLJeDvAqbGEQZTnuosdbnlPfEAJe5n nREMEgGf+Ok5IEpeSBgPPq2nUUJkq9iYR8H+miC0ZYGckOsYUcYnn8d/vgAg7uqKXIifHvGHUBob+ VVauWn5quMfaql1O7esN0wo0WU72gWztSjMiGH83FROiFPlRSu2kUEXmXckEcAC/AklkP3EdzC0+c Z60Ny8c6Ogvy7ebATCVg==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1o1cGh-00GpTr-5p; Wed, 15 Jun 2022 23:17:47 +0000 Received: from ams.source.kernel.org ([145.40.68.75]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1o1cFG-00Goj5-Rn for linux-arm-kernel@lists.infradead.org; Wed, 15 Jun 2022 23:16:20 +0000 Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ams.source.kernel.org (Postfix) with ESMTPS id 8697AB821A6; Wed, 15 Jun 2022 23:16:17 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id C38F8C3411A; Wed, 15 Jun 2022 23:16:15 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1655334976; bh=cAJc7R7bE7xqXWor8RIIlSkD8G16T7DVc9c6nA3MW70=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=hmOWlUMWLuGk93fTZdM2ZA5EUc664xLxgGIuWkZjzVD8k+UAoGCr9oqUMl1F7LLAg i3HapcV1AhKAkGci/Z6vAgi8VTP4f+dh5yNi54R7m/OwImR8UO/C7UrmzOHeEqb2xw DhIZ203TbCbvM4wb3q7187HU6gaAqur25XrZRjRqI8UOPrSO8SDe0kM9KHN0WBKZkI q6QQktpxs4xJp8PPor3mq7uocXF+Ocmjj4Q1l/Wuc0QNRAgIHCLvU+kQUenJJCBHtx w7X54W+JsYCDdgCb2KDU58M6EWLmb2RRY7+YbEhYdMYTX6+JhsV9/qcPpJUr4iGIIG 8Tx63dmqF/FOw== From: Bjorn Helgaas To: Richard Zhu , Lucas Stach , Rob Herring , Mark Brown , Lorenzo Pieralisi , Fabio Estevam , Francesco Dolcini Cc: linux-pci@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, kernel@pengutronix.de, linux-imx@nxp.com, Bjorn Helgaas Subject: [PATCH v12 06/13] PCI: imx6: Collect clock enables in imx6_pcie_clk_enable() Date: Wed, 15 Jun 2022 18:15:44 -0500 Message-Id: <20220615231551.1054753-7-helgaas@kernel.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220615231551.1054753-1-helgaas@kernel.org> References: <20220615231551.1054753-1-helgaas@kernel.org> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220615_161619_255613_B8CA2A0B X-CRM114-Status: GOOD ( 17.03 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org From: Richard Zhu Encapsulate the i.MX PCIe clock enable operations into one standalone function, imx6_pcie_clk_enable(). No functional change intended. [bhelgaas: split pure code moves into separate patches] Link: https://lore.kernel.org/r/1655189942-12678-2-git-send-email-hongxing.zhu@nxp.com Signed-off-by: Richard Zhu Signed-off-by: Bjorn Helgaas Reviewed-by: Lucas Stach --- drivers/pci/controller/dwc/pci-imx6.c | 98 ++++++++++++++++----------- 1 file changed, 58 insertions(+), 40 deletions(-) diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller/dwc/pci-imx6.c index f458461880dc..e36ca08a7c51 100644 --- a/drivers/pci/controller/dwc/pci-imx6.c +++ b/drivers/pci/controller/dwc/pci-imx6.c @@ -600,6 +600,58 @@ static void imx6_pcie_disable_ref_clk(struct imx6_pcie *imx6_pcie) } } +static int imx6_pcie_clk_enable(struct imx6_pcie *imx6_pcie) +{ + struct dw_pcie *pci = imx6_pcie->pci; + struct device *dev = pci->dev; + int ret; + + ret = clk_prepare_enable(imx6_pcie->pcie_phy); + if (ret) { + dev_err(dev, "unable to enable pcie_phy clock\n"); + return ret; + } + + ret = clk_prepare_enable(imx6_pcie->pcie_bus); + if (ret) { + dev_err(dev, "unable to enable pcie_bus clock\n"); + goto err_pcie_bus; + } + + ret = clk_prepare_enable(imx6_pcie->pcie); + if (ret) { + dev_err(dev, "unable to enable pcie clock\n"); + goto err_pcie; + } + + ret = imx6_pcie_enable_ref_clk(imx6_pcie); + if (ret) { + dev_err(dev, "unable to enable pcie ref clock\n"); + goto err_ref_clk; + } + + switch (imx6_pcie->drvdata->variant) { + case IMX8MM: + if (phy_power_on(imx6_pcie->phy)) + dev_err(dev, "unable to power on PHY\n"); + break; + default: + break; + } + /* allow the clocks to stabilize */ + usleep_range(200, 500); + return 0; + +err_ref_clk: + clk_disable_unprepare(imx6_pcie->pcie); +err_pcie: + clk_disable_unprepare(imx6_pcie->pcie_bus); +err_pcie_bus: + clk_disable_unprepare(imx6_pcie->pcie_phy); + + return ret; +} + static void imx6_pcie_clk_disable(struct imx6_pcie *imx6_pcie) { clk_disable_unprepare(imx6_pcie->pcie); @@ -660,7 +712,7 @@ static void imx6_pcie_deassert_core_reset(struct imx6_pcie *imx6_pcie) { struct dw_pcie *pci = imx6_pcie->pci; struct device *dev = pci->dev; - int ret; + int ret, err; if (imx6_pcie->vpcie && !regulator_is_enabled(imx6_pcie->vpcie)) { ret = regulator_enable(imx6_pcie->vpcie); @@ -671,40 +723,12 @@ static void imx6_pcie_deassert_core_reset(struct imx6_pcie *imx6_pcie) } } - ret = clk_prepare_enable(imx6_pcie->pcie_phy); - if (ret) { - dev_err(dev, "unable to enable pcie_phy clock\n"); - goto err_pcie_phy; + err = imx6_pcie_clk_enable(imx6_pcie); + if (err) { + dev_err(dev, "unable to enable pcie clocks: %d\n", err); + goto err_clks; } - ret = clk_prepare_enable(imx6_pcie->pcie_bus); - if (ret) { - dev_err(dev, "unable to enable pcie_bus clock\n"); - goto err_pcie_bus; - } - - ret = clk_prepare_enable(imx6_pcie->pcie); - if (ret) { - dev_err(dev, "unable to enable pcie clock\n"); - goto err_pcie; - } - - ret = imx6_pcie_enable_ref_clk(imx6_pcie); - if (ret) { - dev_err(dev, "unable to enable pcie ref clock\n"); - goto err_ref_clk; - } - - switch (imx6_pcie->drvdata->variant) { - case IMX8MM: - if (phy_power_on(imx6_pcie->phy)) - dev_err(dev, "unable to power on PHY\n"); - break; - default: - break; - } - /* allow the clocks to stabilize */ - usleep_range(200, 500); switch (imx6_pcie->drvdata->variant) { case IMX8MQ: @@ -763,13 +787,7 @@ static void imx6_pcie_deassert_core_reset(struct imx6_pcie *imx6_pcie) return; -err_ref_clk: - clk_disable_unprepare(imx6_pcie->pcie); -err_pcie: - clk_disable_unprepare(imx6_pcie->pcie_bus); -err_pcie_bus: - clk_disable_unprepare(imx6_pcie->pcie_phy); -err_pcie_phy: +err_clks: if (imx6_pcie->vpcie && regulator_is_enabled(imx6_pcie->vpcie) > 0) { ret = regulator_disable(imx6_pcie->vpcie); if (ret)