diff mbox series

ARM: dts: stm32: fix pwr regulators references to use scmi

Message ID 20220624090055.569400-1-etienne.carriere@linaro.org (mailing list archive)
State New, archived
Headers show
Series ARM: dts: stm32: fix pwr regulators references to use scmi | expand

Commit Message

Etienne Carriere June 24, 2022, 9 a.m. UTC
Fixes stm32mp15*-scmi DTS files introduced in [1] to also access PWR
regulators through SCMI service. This is needed since enabling secure
only access to RCC clock and reset controllers also enables secure
access only on PWR voltage regulators reg11, reg18 and usb33 hence
these must also be accessed through SCMI Voltage Domain protocol.
This change applies on commit [2] that already corrects issues from
commit [1].

Cc: Alexandre Torgue <alexandre.torgue@foss.st.com>
Link: [1] https://lore.kernel.org/linux-arm-kernel/20220422150952.20587-7-alexandre.torgue@foss.st.com
Link: [2] https://lore.kernel.org/linux-arm-kernel/20220613071920.5463-1-alexandre.torgue@foss.st.com
Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
---
 arch/arm/boot/dts/stm32mp15-scmi.dtsi      | 52 ++++++++++++++++++++++
 arch/arm/boot/dts/stm32mp157c-dk2-scmi.dts |  1 +
 arch/arm/boot/dts/stm32mp157c-ev1-scmi.dts |  1 +
 3 files changed, 54 insertions(+)

Comments

Alexandre TORGUE July 1, 2022, 11:43 a.m. UTC | #1
Hi Etienne

On 6/24/22 11:00, Etienne Carriere wrote:
> Fixes stm32mp15*-scmi DTS files introduced in [1] to also access PWR
> regulators through SCMI service. This is needed since enabling secure
> only access to RCC clock and reset controllers also enables secure
> access only on PWR voltage regulators reg11, reg18 and usb33 hence
> these must also be accessed through SCMI Voltage Domain protocol.
> This change applies on commit [2] that already corrects issues from
> commit [1].
> 
> Cc: Alexandre Torgue <alexandre.torgue@foss.st.com>
> Link: [1] https://lore.kernel.org/linux-arm-kernel/20220422150952.20587-7-alexandre.torgue@foss.st.com
> Link: [2] https://lore.kernel.org/linux-arm-kernel/20220613071920.5463-1-alexandre.torgue@foss.st.com
> Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
> ---

Applied in stm32-fixes.

Thanks
Alex
Etienne Carriere July 1, 2022, 11:58 a.m. UTC | #2
Thanks Alex,

By the way, my review tags for other fixes to the scmi DTS files [1],
[2] and [3]:
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
Tested-by: Etienne Carriere <etienne.carriere@linaro.org>
These are needed for a consistent kernel configuration of these boards.

Br,
etienne

[1] https://lore.kernel.org/lkml/20220624092715.1397827-2-gabriel.fernandez@foss.st.com/
[2] https://lore.kernel.org/lkml/20220624092715.1397827-3-gabriel.fernandez@foss.st.com/
[3] https://lore.kernel.org/lkml/20220624092715.1397827-4-gabriel.fernandez@foss.st.com/

On Fri, 1 Jul 2022 at 13:44, Alexandre TORGUE
<alexandre.torgue@foss.st.com> wrote:
>
> Hi Etienne
>
> On 6/24/22 11:00, Etienne Carriere wrote:
> > Fixes stm32mp15*-scmi DTS files introduced in [1] to also access PWR
> > regulators through SCMI service. This is needed since enabling secure
> > only access to RCC clock and reset controllers also enables secure
> > access only on PWR voltage regulators reg11, reg18 and usb33 hence
> > these must also be accessed through SCMI Voltage Domain protocol.
> > This change applies on commit [2] that already corrects issues from
> > commit [1].
> >
> > Cc: Alexandre Torgue <alexandre.torgue@foss.st.com>
> > Link: [1] https://lore.kernel.org/linux-arm-kernel/20220422150952.20587-7-alexandre.torgue@foss.st.com
> > Link: [2] https://lore.kernel.org/linux-arm-kernel/20220613071920.5463-1-alexandre.torgue@foss.st.com
> > Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
> > ---
>
> Applied in stm32-fixes.
>
> Thanks
> Alex
Alexandre TORGUE July 1, 2022, 12:06 p.m. UTC | #3
On 7/1/22 13:58, Etienne Carriere wrote:
> Thanks Alex,
> 
> By the way, my review tags for other fixes to the scmi DTS files [1],
> [2] and [3]:
> Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
> Tested-by: Etienne Carriere <etienne.carriere@linaro.org>
> These are needed for a consistent kernel configuration of these boards.
> 

Sorry Etienne, I just sent it. But thanks for your tests ;)

Alex

> Br,
> etienne
> 
> [1] https://lore.kernel.org/lkml/20220624092715.1397827-2-gabriel.fernandez@foss.st.com/
> [2] https://lore.kernel.org/lkml/20220624092715.1397827-3-gabriel.fernandez@foss.st.com/
> [3] https://lore.kernel.org/lkml/20220624092715.1397827-4-gabriel.fernandez@foss.st.com/
> 
> On Fri, 1 Jul 2022 at 13:44, Alexandre TORGUE
> <alexandre.torgue@foss.st.com> wrote:
>>
>> Hi Etienne
>>
>> On 6/24/22 11:00, Etienne Carriere wrote:
>>> Fixes stm32mp15*-scmi DTS files introduced in [1] to also access PWR
>>> regulators through SCMI service. This is needed since enabling secure
>>> only access to RCC clock and reset controllers also enables secure
>>> access only on PWR voltage regulators reg11, reg18 and usb33 hence
>>> these must also be accessed through SCMI Voltage Domain protocol.
>>> This change applies on commit [2] that already corrects issues from
>>> commit [1].
>>>
>>> Cc: Alexandre Torgue <alexandre.torgue@foss.st.com>
>>> Link: [1] https://lore.kernel.org/linux-arm-kernel/20220422150952.20587-7-alexandre.torgue@foss.st.com
>>> Link: [2] https://lore.kernel.org/linux-arm-kernel/20220613071920.5463-1-alexandre.torgue@foss.st.com
>>> Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
>>> ---
>>
>> Applied in stm32-fixes.
>>
>> Thanks
>> Alex
diff mbox series

Patch

diff --git a/arch/arm/boot/dts/stm32mp15-scmi.dtsi b/arch/arm/boot/dts/stm32mp15-scmi.dtsi
index e90cf3acd0b3..d2afb6667479 100644
--- a/arch/arm/boot/dts/stm32mp15-scmi.dtsi
+++ b/arch/arm/boot/dts/stm32mp15-scmi.dtsi
@@ -27,6 +27,37 @@  scmi_reset: protocol@16 {
 				reg = <0x16>;
 				#reset-cells = <1>;
 			};
+
+			scmi_voltd: protocol@17 {
+				reg = <0x17>;
+
+				scmi_reguls: regulators {
+					#address-cells = <1>;
+					#size-cells = <0>;
+
+					scmi_reg11: reg11@0 {
+						reg = <0>;
+						regulator-name = "reg11";
+						regulator-min-microvolt = <1100000>;
+						regulator-max-microvolt = <1100000>;
+					};
+
+					scmi_reg18: reg18@1 {
+						voltd-name = "reg18";
+						reg = <1>;
+						regulator-name = "reg18";
+						regulator-min-microvolt = <1800000>;
+						regulator-max-microvolt = <1800000>;
+					};
+
+					scmi_usb33: usb33@2 {
+						reg = <2>;
+						regulator-name = "usb33";
+						regulator-min-microvolt = <3300000>;
+						regulator-max-microvolt = <3300000>;
+					};
+				};
+			};
 		};
 	};
 
@@ -45,3 +76,24 @@  scmi_shm: scmi-sram@0 {
 		};
 	};
 };
+
+&reg11 {
+	status = "disabled";
+};
+
+&reg18 {
+	status = "disabled";
+};
+
+&usb33 {
+	status = "disabled";
+};
+
+&usbotg_hs {
+	usb33d-supply = <&scmi_usb33>;
+};
+
+&usbphyc {
+	vdda1v1-supply = <&scmi_reg11>;
+	vdda1v8-supply = <&scmi_reg18>;
+};
diff --git a/arch/arm/boot/dts/stm32mp157c-dk2-scmi.dts b/arch/arm/boot/dts/stm32mp157c-dk2-scmi.dts
index 03226a596904..97e4f94b0a24 100644
--- a/arch/arm/boot/dts/stm32mp157c-dk2-scmi.dts
+++ b/arch/arm/boot/dts/stm32mp157c-dk2-scmi.dts
@@ -35,6 +35,7 @@  &cryp1 {
 };
 
 &dsi {
+	phy-dsi-supply = <&scmi_reg18>;
 	clocks = <&rcc DSI_K>, <&scmi_clk CK_SCMI_HSE>, <&rcc DSI_PX>;
 };
 
diff --git a/arch/arm/boot/dts/stm32mp157c-ev1-scmi.dts b/arch/arm/boot/dts/stm32mp157c-ev1-scmi.dts
index 7842384ddbe4..3b9dd6f4ccc9 100644
--- a/arch/arm/boot/dts/stm32mp157c-ev1-scmi.dts
+++ b/arch/arm/boot/dts/stm32mp157c-ev1-scmi.dts
@@ -36,6 +36,7 @@  &cryp1 {
 };
 
 &dsi {
+	phy-dsi-supply = <&scmi_reg18>;
 	clocks = <&rcc DSI_K>, <&scmi_clk CK_SCMI_HSE>, <&rcc DSI_PX>;
 };