From patchwork Fri Jun 24 15:06:34 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ard Biesheuvel X-Patchwork-Id: 12894744 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 5BD2BC433EF for ; Fri, 24 Jun 2022 15:08:57 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=bHJ5hP+6pHoKvlq9Yux9cM82pZ6FcpA7jpI9REv3RXA=; b=pshbUmiyMEzZB3 O3eVupSRfWdwCBAfKnjHlI4Oo0uo6M5vWmH7ERGDlVhd+Qt2qidyh/7Xz65WOtwf0rHmzhqhvup4c 9sndd5bYsk6GgZQq7Xc2mhcwMCLnbUMIpViq/pPffRGJlwwq7v5v7crBdX4ttReDNIOZJHDq+FB5W xVIq30w85zX/4f1dSNqV8YzY+ej4GFlY1iz1pouyMJVnLSlFpyYApnQlGQn2H8qzpkEFMu0VO6j/5 uZCgzUxSo7es4GaNvaTQXsamLyOuscxGf+ZOiN7lMqKHDnTo9wE1+PMhAmhD7WJP9UpRAPQY176xU ujHDIXuLdbOjbU83VTWQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1o4kuW-002iXn-MF; Fri, 24 Jun 2022 15:07:52 +0000 Received: from sin.source.kernel.org ([2604:1380:40e1:4800::1]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1o4ku2-002iMx-WC for linux-arm-kernel@lists.infradead.org; Fri, 24 Jun 2022 15:07:24 +0000 Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by sin.source.kernel.org (Postfix) with ESMTPS id 6B75CCE2AB2; Fri, 24 Jun 2022 15:07:20 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id D1D94C36AE3; Fri, 24 Jun 2022 15:07:16 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1656083238; bh=TvugYq/yTY2PK7+ouhMEJORa44d53Jx+xs/sbOdz64w=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=E55bVQgqIrkSRyXm5zzk6SeEXrkyb+Nf1V7zp0R7r0R+cFvOIJQ0iCOZiD2WGybaz AATuSXxEJJ2+npTWU/ul/2bGNHL39i+Etj26S/iq2FO+1OMVrJqbDEOE5nwU5vsIDb d0EOMLrHWHow+rttck4U+R4vCnVnCdsT4HpZF3qzGDvfCYw3JbBCkvxTUt83dTNM5A ayVm6pnb+fxnV2h/n/xOglMxoeuatMlyNp+IgLRMTfBIum/9VKm2enVKzi6oSUJk36 LgCKJa1Aii80YAq/v+IkewsIhQZVHheNdJQQqXravkgwOhjcGN29ClX8EEd6IIDygs AAz65jcW3hAiw== From: Ard Biesheuvel To: linux-arm-kernel@lists.infradead.org Cc: Ard Biesheuvel , Marc Zyngier , Will Deacon , Mark Rutland , Kees Cook , Catalin Marinas , Mark Brown , Anshuman Khandual Subject: [PATCH v5 04/21] arm64: head: drop idmap_ptrs_per_pgd Date: Fri, 24 Jun 2022 17:06:34 +0200 Message-Id: <20220624150651.1358849-5-ardb@kernel.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220624150651.1358849-1-ardb@kernel.org> References: <20220624150651.1358849-1-ardb@kernel.org> MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=2669; h=from:subject; bh=TvugYq/yTY2PK7+ouhMEJORa44d53Jx+xs/sbOdz64w=; b=owEB7QES/pANAwAKAcNPIjmS2Y8kAcsmYgBitdLteztav2iQxjxowPu10w9s/7VbxZMQvgzF+aCt MMKJ09iJAbMEAAEKAB0WIQT72WJ8QGnJQhU3VynDTyI5ktmPJAUCYrXS7QAKCRDDTyI5ktmPJODIC/ 9UUJNKW8Ek1a315oLKRzkWpnRaxpFxTOagWhUq57/Biqhcrm4qnDGjQtjGrhzWjcyPf0qVKjco8RfV u4JltK0uzIrhYcw0lDW0m+pPqhtLkH5KIQwVij7SBAXOsDKNEsqEKW+seufl3oLRJ4f1IV88aMhMLR zzcmoxGNGSeb6Ll6Z8csmiFUPRQwVGhMn9CWPeyk5dZe8LbDapydRcKIIfe3Chu5acKEOIBcaPENZN 3cx5g4yon8zyoPcs0CiMeOsSukJd++WrYBIfifRqtzNtHdeWe+hZxshCiqDxYusKYIg2vn6CY6Rw4N dJJ015eiKhwrqxnJQ2ezaTwT9x/wkkROfbTOkHSFGFfIOlcTptDfnUWjmYeFooKZHtZrCTvmU/ime+ wfYiiifsaSPID4rn87Rr2zc6xdtermgLgkV96oeHVG3ySmwe5W7qPjk4e807y4x1ruwzdhgywngk/v H91TbH5SP/SQUAm3LF8rGWHKBFmSePYLPFed3RNedo6A8= X-Developer-Key: i=ardb@kernel.org; a=openpgp; fpr=F43D03328115A198C90016883D200E9CA6329909 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220624_080723_426207_E8594BFE X-CRM114-Status: GOOD ( 14.91 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org The assignment of idmap_ptrs_per_pgd lacks any cache invalidation, even though it is updated with the MMU and caches disabled. However, we never bother to read the value again except in the very next instruction, and so we can just drop the variable entirely. Signed-off-by: Ard Biesheuvel Reviewed-by: Anshuman Khandual Acked-by: Mark Rutland --- arch/arm64/include/asm/mmu_context.h | 1 - arch/arm64/kernel/head.S | 7 +++---- arch/arm64/mm/mmu.c | 1 - 3 files changed, 3 insertions(+), 6 deletions(-) diff --git a/arch/arm64/include/asm/mmu_context.h b/arch/arm64/include/asm/mmu_context.h index 6ac0086ebb1a..7b387c3b312a 100644 --- a/arch/arm64/include/asm/mmu_context.h +++ b/arch/arm64/include/asm/mmu_context.h @@ -61,7 +61,6 @@ static inline void cpu_switch_mm(pgd_t *pgd, struct mm_struct *mm) * physical memory, in which case it will be smaller. */ extern int idmap_t0sz; -extern u64 idmap_ptrs_per_pgd; /* * Ensure TCR.T0SZ is set to the provided value. diff --git a/arch/arm64/kernel/head.S b/arch/arm64/kernel/head.S index 7f361bc72d12..53126a35d73c 100644 --- a/arch/arm64/kernel/head.S +++ b/arch/arm64/kernel/head.S @@ -300,6 +300,7 @@ SYM_FUNC_START_LOCAL(__create_page_tables) * range in that case, and configure an additional translation level * if needed. */ + mov x4, #PTRS_PER_PGD idmap_get_t0sz x5 cmp x5, TCR_T0SZ(VA_BITS_MIN) // default T0SZ small enough? b.ge 1f // .. then skip VA range extension @@ -319,18 +320,16 @@ SYM_FUNC_START_LOCAL(__create_page_tables) #error "Mismatch between VA_BITS and page size/number of translation levels" #endif - mov x4, EXTRA_PTRS - create_table_entry x0, x3, EXTRA_SHIFT, x4, x5, x6 + mov x2, EXTRA_PTRS + create_table_entry x0, x3, EXTRA_SHIFT, x2, x5, x6 #else /* * If VA_BITS == 48, we don't have to configure an additional * translation level, but the top-level table has more entries. */ mov x4, #1 << (PHYS_MASK_SHIFT - PGDIR_SHIFT) - str_l x4, idmap_ptrs_per_pgd, x5 #endif 1: - ldr_l x4, idmap_ptrs_per_pgd adr_l x6, __idmap_text_end // __pa(__idmap_text_end) map_memory x0, x1, x3, x6, x7, x3, x4, x10, x11, x12, x13, x14 diff --git a/arch/arm64/mm/mmu.c b/arch/arm64/mm/mmu.c index f875c4954e22..3be0e9f69406 100644 --- a/arch/arm64/mm/mmu.c +++ b/arch/arm64/mm/mmu.c @@ -44,7 +44,6 @@ #define NO_EXEC_MAPPINGS BIT(2) /* assumes FEAT_HPDS is not used */ int idmap_t0sz __ro_after_init; -u64 idmap_ptrs_per_pgd = PTRS_PER_PGD; #if VA_BITS > 48 u64 vabits_actual __ro_after_init = VA_BITS_MIN;