| Message ID | 20220627005210.6473-3-chanho61.park@samsung.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | fixes for exynosautov9 clock | expand |
On 27/06/2022 02:52, Chanho Park wrote: > "gout_peric0_pclk_1" and "gout_peric1_pclk_1" should be added to peric0 > and peric1 respectively. Where is exactly the bug? The commit msg suggests that they were added to different block, but there is no code removal. > > Fixes: f2dd366992d0 ("clk: samsung: exynosautov9: add cmu_peric0 clock support") > Fixes: b35f27fe73d8 ("clk: samsung: exynosautov9: add cmu_peric1 clock support") > Signed-off-by: Chanho Park <chanho61.park@samsung.com> > --- > drivers/clk/samsung/clk-exynosautov9.c | 8 ++++++++ > 1 file changed, 8 insertions(+) Best regards, Krzysztof
> Subject: Re: [PATCH 2/3] clk: samsung: exynosautov9: add missing gate clks > for peric0/c1 > > On 27/06/2022 02:52, Chanho Park wrote: > > "gout_peric0_pclk_1" and "gout_peric1_pclk_1" should be added to > > peric0 and peric1 respectively. > > Where is exactly the bug? The commit msg suggests that they were added to > different block, but there is no code removal. I thought they should be added from previous patch because clock IDs were existing without implementations. I can drop fixes tags next patchset. Best Regards, Chanho Park
On 28/06/2022 04:10, Chanho Park wrote: >> Subject: Re: [PATCH 2/3] clk: samsung: exynosautov9: add missing gate clks >> for peric0/c1 >> >> On 27/06/2022 02:52, Chanho Park wrote: >>> "gout_peric0_pclk_1" and "gout_peric1_pclk_1" should be added to >>> peric0 and peric1 respectively. >> >> Where is exactly the bug? The commit msg suggests that they were added to >> different block, but there is no code removal. > > I thought they should be added from previous patch because clock IDs were existing without implementations. > I can drop fixes tags next patchset. The clock IDs as bindings can be added upfront - it's independent from implementation. Please drop the fixes. Best regards, Krzysztof
diff --git a/drivers/clk/samsung/clk-exynosautov9.c b/drivers/clk/samsung/clk-exynosautov9.c index d9e1f8e4a7b4..c5a4e1bee711 100644 --- a/drivers/clk/samsung/clk-exynosautov9.c +++ b/drivers/clk/samsung/clk-exynosautov9.c @@ -1330,6 +1330,10 @@ static const struct samsung_gate_clock peric0_gate_clks[] __initconst = { "mout_peric0_bus_user", CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_0, 21, 0, 0), + GATE(CLK_GOUT_PERIC0_PCLK_1, "gout_peric0_pclk_1", + "mout_peric0_bus_user", + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_1, + 21, 0, 0), GATE(CLK_GOUT_PERIC0_PCLK_2, "gout_peric0_pclk_2", "mout_peric0_bus_user", CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_2, @@ -1581,6 +1585,10 @@ static const struct samsung_gate_clock peric1_gate_clks[] __initconst = { "mout_peric1_bus_user", CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_0, 21, 0, 0), + GATE(CLK_GOUT_PERIC1_PCLK_1, "gout_peric1_pclk_1", + "mout_peric1_bus_user", + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_1, + 21, 0, 0), GATE(CLK_GOUT_PERIC1_PCLK_2, "gout_peric1_pclk_2", "mout_peric1_bus_user", CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_2,
"gout_peric0_pclk_1" and "gout_peric1_pclk_1" should be added to peric0 and peric1 respectively. Fixes: f2dd366992d0 ("clk: samsung: exynosautov9: add cmu_peric0 clock support") Fixes: b35f27fe73d8 ("clk: samsung: exynosautov9: add cmu_peric1 clock support") Signed-off-by: Chanho Park <chanho61.park@samsung.com> --- drivers/clk/samsung/clk-exynosautov9.c | 8 ++++++++ 1 file changed, 8 insertions(+)