diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 5112f493f494..831401e5d021 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -400,7 +400,8 @@ dtb-$(CONFIG_ARCH_MMP) += \
 	mmp3-dell-ariel.dtb
 dtb-$(CONFIG_ARCH_MPS2) += \
 	mps2-an385.dtb \
-	mps2-an399.dtb
+	mps2-an399.dtb \
+	mps3-an536.dtb
 dtb-$(CONFIG_ARCH_MOXART) += \
 	moxart-uc7112lx.dtb
 dtb-$(CONFIG_ARCH_SD5203) += \
diff --git a/arch/arm/boot/dts/mps3-an536.dts b/arch/arm/boot/dts/mps3-an536.dts
new file mode 100644
index 000000000000..240c5bb46471
--- /dev/null
+++ b/arch/arm/boot/dts/mps3-an536.dts
@@ -0,0 +1,135 @@
+// SPDX-License-Identifier: GPL-2.0 or MIT
+/*
+ * Copyright (c) 2022, Arm Limited. All rights reserved.
+ *
+ * Author: Vladimir Murzin <vladimir.murzin@arm.com>
+ */
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+/dts-v1/;
+
+
+/ {
+	model = "ARM MPS3 Application Note 536";
+	compatible = "arm,mps3","arm,mps2";
+	interrupt-parent = <&gic>;
+	#address-cells = <1>;
+	#size-cells = <1>;
+
+	aliases {
+		serial0 = &uart0;
+		serial1 = &uart1;
+	};
+
+	chosen {
+		bootargs = "earlycon";
+		stdout-path = "serial0:115200n8";
+	};
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu@0 {
+			device_type = "cpu";
+			compatible = "arm,armv8";
+			reg = <0>;
+		};
+	};
+
+	memory@20000000 {
+		device_type = "memory";
+		reg = <0x20000000 0x20000000>;
+	};
+
+	clk-osc0 {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <24000000>;
+	};
+
+	sysclk: clk-osc1 {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <50000000>;
+	};
+
+	gic: interrupt-controller@f0000000 {
+		compatible = "arm,gic-v3";
+		#interrupt-cells = <3>;
+		interrupt-controller;
+		reg = <0xf0000000 0x10000>, // GICD
+		      <0xf0100000 0x40000>; // GICR
+		interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
+	};
+
+	timer {
+	      compatible = "arm,armv8-timer";
+              interrupts = <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
+                           <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>;
+              interrupt-names = "phys", "virt";
+        };
+
+
+	soc {
+		compatible = "simple-bus";
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges;
+
+		uart0: serial@e0205000 {
+			compatible = "arm,mps2-uart";
+			reg = <0xe0205000 0x1000>;
+			interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&sysclk>;
+		};
+
+		uart1: serial@e0206000 {
+			compatible = "arm,mps2-uart";
+			reg = <0xe0206000 0x1000>;
+			interrupts = <GIC_SPI 7  IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 8  IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&sysclk>;
+		};
+
+	};
+
+	fpga@e0200000 {
+		compatible = "simple-bus";
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges = <0 0xe0200000 0x3000>;
+
+		fpgaio@2000 {
+			compatible = "syscon", "simple-mfd";
+			reg = <0x2000 0x10>;
+			ranges = <0x0 0x2000 0x10>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			led0,0 {
+				compatible = "register-bit-led";
+				reg = <0x00 0x04>;
+				offset = <0x00>;
+				mask = <0x01>;
+				label = "userled:0";
+				linux,default-trigger = "heartbeat";
+				default-state = "on";
+			};
+
+			led0,1 {
+				compatible = "register-bit-led";
+				reg = <0x00 0x04>;
+				offset = <0x00>;
+				mask = <0x02>;
+				label = "userled:1";
+				linux,default-trigger = "usr";
+				default-state = "off";
+			};
+		};
+	};
+};
diff --git a/arch/arm/mach-versatile/Kconfig b/arch/arm/mach-versatile/Kconfig
index 18643af4f3e1..94c26bd7d3b9 100644
--- a/arch/arm/mach-versatile/Kconfig
+++ b/arch/arm/mach-versatile/Kconfig
@@ -327,19 +327,21 @@ config ARCH_VEXPRESS_TC2_PM
 endif
 
 menuconfig ARCH_MPS2
-	bool "ARM MPS2 family"
-	depends on ARM_SINGLE_ARMV7M
+	bool "ARM MPS2/MPS3 family"
+	depends on ARM_SINGLE_ARMV7M || ARM_SINGLE_ARMV7R
 	select ARM_AMBA
 	select CLKSRC_MPS2
 	help
-         Support for Cortex-M Prototyping System (or V2M-MPS2) which comes
-         with a range of available cores like Cortex-M3/M4/M7.
+	  Support for ARM MPS2/MPS3 paltform which comes with a range
+	  of available cores from Cortex-M and Cortex-R families.
 
-         Please, note that depends which Application Note is used memory map
-         for the platform may vary, so adjustment of RAM base might be needed.
+	  Please, note that depends which Application Note is used memory map
+	  for the platform may vary, so adjustment of RAM base might be needed.
 
 if ARCH_MPS2
 
+if ARM_SINGLE_ARMV7M
+
 config MACH_MPS2_AN385
 	bool "ARM MPS2 Application Note 385"
 	default y
@@ -356,4 +358,17 @@ config MACH_MPS2_AN400
 	bool "ARM MPS2 Application Note 400"
 	default y
 
+endif # ARMv7-M
+
+if ARM_SINGLE_ARMV7R
+
+config MACH_MPS3_AN536
+       bool "ARM MPS3 Application Note 536"
+       default y
+       select ARM_GIC_V3
+       select HAVE_ARM_ARCH_TIMER
+
+endif # ARMv7-R
+
+
 endif # MPS2
diff --git a/arch/arm/mach-versatile/v2m-mps2.c b/arch/arm/mach-versatile/v2m-mps2.c
index 5b50d8e95cd7..3a6c3bdfefd0 100644
--- a/arch/arm/mach-versatile/v2m-mps2.c
+++ b/arch/arm/mach-versatile/v2m-mps2.c
@@ -9,9 +9,10 @@
 
 static const char *const mps2_compat[] __initconst = {
 	"arm,mps2",
+	"arm,mps3",
 	NULL
 };
 
-DT_MACHINE_START(MPS2DT, "MPS2 (Device Tree Support)")
+DT_MACHINE_START(MPS2DT, "MPS2/MPS3 (Device Tree Support)")
 	.dt_compat = mps2_compat,
 MACHINE_END
