| Message ID | 20220630090157.29486-2-xiangsheng.hou@mediatek.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | arm64: dts: mt8173: Fix nor flash node | expand |
On 30/06/2022 11:01, Xiangsheng Hou wrote: > Add axi clock since the driver change to DMA mode which need > to enable axi clock. And change spi clock to 26MHz as default. > > Signed-off-by: Xiangsheng Hou <xiangsheng.hou@mediatek.com> Applied, thanks! > --- > arch/arm64/boot/dts/mediatek/mt8173.dtsi | 7 +++++-- > 1 file changed, 5 insertions(+), 2 deletions(-) > > diff --git a/arch/arm64/boot/dts/mediatek/mt8173.dtsi b/arch/arm64/boot/dts/mediatek/mt8173.dtsi > index 40d7b47fc52e..e603170100af 100644 > --- a/arch/arm64/boot/dts/mediatek/mt8173.dtsi > +++ b/arch/arm64/boot/dts/mediatek/mt8173.dtsi > @@ -790,9 +790,12 @@ thermal: thermal@1100b000 { > nor_flash: spi@1100d000 { > compatible = "mediatek,mt8173-nor"; > reg = <0 0x1100d000 0 0xe0>; > + assigned-clocks = <&topckgen CLK_TOP_SPI_SEL>; > + assigned-clock-parents = <&clk26m>; > clocks = <&pericfg CLK_PERI_SPI>, > - <&topckgen CLK_TOP_SPINFI_IFR_SEL>; > - clock-names = "spi", "sf"; > + <&topckgen CLK_TOP_SPINFI_IFR_SEL>, > + <&pericfg CLK_PERI_NFI>; > + clock-names = "spi", "sf", "axi"; > #address-cells = <1>; > #size-cells = <0>; > status = "disabled";
Hi Matthias, On Thu, 2022-07-07 at 16:43 +0200, Matthias Brugger wrote: > > On 30/06/2022 11:01, Xiangsheng Hou wrote: > > Add axi clock since the driver change to DMA mode which need > > to enable axi clock. And change spi clock to 26MHz as default. > > > > Signed-off-by: Xiangsheng Hou <xiangsheng.hou@mediatek.com> > > Applied, thanks! > I will send a new patch v3 since there need a change in [PATCH v2 2/2] by review. Thanks Xiangsheng Hou
On 08/07/2022 03:40, xiangsheng.hou wrote: > Hi Matthias, > > On Thu, 2022-07-07 at 16:43 +0200, Matthias Brugger wrote: >> >> On 30/06/2022 11:01, Xiangsheng Hou wrote: >>> Add axi clock since the driver change to DMA mode which need >>> to enable axi clock. And change spi clock to 26MHz as default. >>> >>> Signed-off-by: Xiangsheng Hou <xiangsheng.hou@mediatek.com> >> >> Applied, thanks! >> > I will send a new patch v3 since there need a change in [PATCH v2 2/2] > by review. > Thanks from letting me know. From what I can see, 1/2 in v3 did not change, so as I already applied it, you could have dropped it from the series. Please correct me if I'm wrong. Best regards, Matthias
Hi Matthias, On Fri, 2022-07-08 at 10:22 +0200, Matthias Brugger wrote: > > On 08/07/2022 03:40, xiangsheng.hou wrote: > > Hi Matthias, > > > > On Thu, 2022-07-07 at 16:43 +0200, Matthias Brugger wrote: > > > > > > On 30/06/2022 11:01, Xiangsheng Hou wrote: > > > > Add axi clock since the driver change to DMA mode which need > > > > to enable axi clock. And change spi clock to 26MHz as default. > > > > > > > > Signed-off-by: Xiangsheng Hou <xiangsheng.hou@mediatek.com> > > > > > > Applied, thanks! > > > > > > > I will send a new patch v3 since there need a change in [PATCH v2 > > 2/2] > > by review. > > > > Thanks from letting me know. From what I can see, 1/2 in v3 did not > change, so > as I already applied it, you could have dropped it from the series. > > Please correct me if I'm wrong. > Yes, you are right and I will drop it if there will have next series. Thanks Xiangsheng Hou
diff --git a/arch/arm64/boot/dts/mediatek/mt8173.dtsi b/arch/arm64/boot/dts/mediatek/mt8173.dtsi index 40d7b47fc52e..e603170100af 100644 --- a/arch/arm64/boot/dts/mediatek/mt8173.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8173.dtsi @@ -790,9 +790,12 @@ thermal: thermal@1100b000 { nor_flash: spi@1100d000 { compatible = "mediatek,mt8173-nor"; reg = <0 0x1100d000 0 0xe0>; + assigned-clocks = <&topckgen CLK_TOP_SPI_SEL>; + assigned-clock-parents = <&clk26m>; clocks = <&pericfg CLK_PERI_SPI>, - <&topckgen CLK_TOP_SPINFI_IFR_SEL>; - clock-names = "spi", "sf"; + <&topckgen CLK_TOP_SPINFI_IFR_SEL>, + <&pericfg CLK_PERI_NFI>; + clock-names = "spi", "sf", "axi"; #address-cells = <1>; #size-cells = <0>; status = "disabled";
Add axi clock since the driver change to DMA mode which need to enable axi clock. And change spi clock to 26MHz as default. Signed-off-by: Xiangsheng Hou <xiangsheng.hou@mediatek.com> --- arch/arm64/boot/dts/mediatek/mt8173.dtsi | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-)