From patchwork Mon Jul 4 08:11:39 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mike Leach X-Patchwork-Id: 12904833 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 6FFEDC433EF for ; Mon, 4 Jul 2022 08:13:59 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:MIME-Version:List-Subscribe:List-Help: List-Post:List-Archive:List-Unsubscribe:List-Id:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=mdrVHsDdvtMoEMpLbnKEHFsrnVT08x0HR99vG947BAE=; b=fLHSlzpnuu7c+T rw4d7JIhXi8user5xi02zuVfvGe03gbFcT9cpMEdb3cywrLVGdcLDGeL1O2hTPjUNPOuvZBecllS1 z737LydeKT7RDrM2eonKYM88yBOTqJME6qKTs+xdYPZzzRr+IcProh8LamVVTIzOaI9he3XUJmHHt wkduezW0U+o3WMegpJjA+QD3FFZ4KhS0w9Fg7lD7f2/ltMj8Jyw38mH7ycq1Ld8n9nHNWzgXyl6QD +ajLNTtGKDiIngrPdIYNZc5CpzdLQAUTRW5XmfOJ3150cSE8XzXjCIGJl8s+OB+UIPlOeIqqPh/rL IErQf8MFfOx/6EY9znMg==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1o8HCO-005yDi-HR; Mon, 04 Jul 2022 08:12:53 +0000 Received: from mail-wm1-x32f.google.com ([2a00:1450:4864:20::32f]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1o8HBY-005xld-0g for linux-arm-kernel@lists.infradead.org; Mon, 04 Jul 2022 08:12:04 +0000 Received: by mail-wm1-x32f.google.com with SMTP id l68so4897239wml.3 for ; Mon, 04 Jul 2022 01:11:55 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=ChF7YhZJ5oK75QeSz9xjFEI1oMT1B8ivnJmEVxe44YU=; b=KHXoITi0VlpeFAc8mJ41i/+VC2MOXFq3PO13PX0hhyD6csdOI5JyfnQ0JCf45ShCfK yihaboRiHuf/MuarutvS7tkoTe7DbxKFNvlqmtJEIKEYdB0AbaS0CnR4ms8x7RLT0y7A Wqr17+DQNb3tbvrzs44QDCk3zGNpU7Ldwp81P7PQFUrsLUNX8Ka9scUWs6NPynzucj7V x20GHD5CtVmBbEHtc8nIGpwvz4hEeZ9tKvpEnuQimFK40Os5d4J3fq/ttkHbOv+h6398 IGMb7UiUqIi/SqXAUh3Rjx9+HyaahAlYcCydH3fp1gsriIpWdZTHYAS4H94insYDxPdL SB2g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=ChF7YhZJ5oK75QeSz9xjFEI1oMT1B8ivnJmEVxe44YU=; b=aSn7TNe0og9BepURjPcBqFsnFKpEXVq+4jkbFt+R6RdN7vOyaf3StNZPxk7KwR3krH MiFIqlfd1jTrGLr5CuJdw9bnj4D+ABFsTORnNO0vic5q/NQTkTLdBxoAfdX4Yv6SMWvu Q6+C5trI28k4Z7rPGonRgkQgQmGS6HRC7gV7ctK9+TaFFwENBpz70rhVhv/CnF/2QeGv HSPtF82L7PG7UaRKt+L/d+F2cp/KpiUp63gDgtCGkGfyHuv38TZIw550bUVNiE5/6XPR Zy5/2JmQd/c8ZBdgXnb1WXqEnuWgo5uwBZh2GdqecUIcyQI4QZlLIfNtq0btO2mpZdqy NFIA== X-Gm-Message-State: AJIora+fPdF/Qw5W5574tMwnUPdqhfqHNFPBS4zjGzb48vb+ikEGJUKX 0WrZq075syhk7U/cvvoOT1M9qw== X-Google-Smtp-Source: AGRyM1u0JcpNIODBc3BhqBED6dntz8ygCUA0VYPXOsX8sMEhi3g5Lq7sdG+kcp3kb4yLdDgsAKYylA== X-Received: by 2002:a05:600c:3481:b0:3a1:918d:6719 with SMTP id a1-20020a05600c348100b003a1918d6719mr14506687wmq.35.1656922314833; Mon, 04 Jul 2022 01:11:54 -0700 (PDT) Received: from linaro.org ([2a00:23c5:6809:2201:c4c4:4ed1:ae43:27f2]) by smtp.gmail.com with ESMTPSA id u3-20020adfdd43000000b0021d650e4df4sm4388276wrm.87.2022.07.04.01.11.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 04 Jul 2022 01:11:54 -0700 (PDT) From: Mike Leach To: suzuki.poulose@arm.com, coresight@lists.linaro.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Cc: mathieu.poirier@linaro.org, peterz@infradead.org, mingo@redhat.com, acme@kernel.org, linux-perf-users@vger.kernel.org, leo.yan@linaro.org, quic_jinlmao@quicinc.com, Mike Leach Subject: [PATCH v2 03/13] coresight: stm: Update STM driver to use Trace ID API Date: Mon, 4 Jul 2022 09:11:39 +0100 Message-Id: <20220704081149.16797-4-mike.leach@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20220704081149.16797-1-mike.leach@linaro.org> References: <20220704081149.16797-1-mike.leach@linaro.org> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220704_011200_112137_6FB5B7B7 X-CRM114-Status: GOOD ( 21.12 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Updates the STM driver to use the trace ID allocation API. This uses the _system_id calls to allocate an ID on device poll, and release on device remove. The sysfs access to the STMTRACEIDR register has been changed from RW to RO. Having this value as writable is not appropriate for the new Trace ID scheme - and had potential to cause errors in the previous scheme if values clashed with other sources. Signed-off-by: Mike Leach Reviewed-by: Suzuki K Poulose --- drivers/hwtracing/coresight/coresight-stm.c | 41 +++++++-------------- 1 file changed, 14 insertions(+), 27 deletions(-) diff --git a/drivers/hwtracing/coresight/coresight-stm.c b/drivers/hwtracing/coresight/coresight-stm.c index bb14a3a8a921..9ef3e923a930 100644 --- a/drivers/hwtracing/coresight/coresight-stm.c +++ b/drivers/hwtracing/coresight/coresight-stm.c @@ -31,6 +31,7 @@ #include #include "coresight-priv.h" +#include "coresight-trace-id.h" #define STMDMASTARTR 0xc04 #define STMDMASTOPR 0xc08 @@ -615,24 +616,7 @@ static ssize_t traceid_show(struct device *dev, val = drvdata->traceid; return sprintf(buf, "%#lx\n", val); } - -static ssize_t traceid_store(struct device *dev, - struct device_attribute *attr, - const char *buf, size_t size) -{ - int ret; - unsigned long val; - struct stm_drvdata *drvdata = dev_get_drvdata(dev->parent); - - ret = kstrtoul(buf, 16, &val); - if (ret) - return ret; - - /* traceid field is 7bit wide on STM32 */ - drvdata->traceid = val & 0x7f; - return size; -} -static DEVICE_ATTR_RW(traceid); +static DEVICE_ATTR_RO(traceid); #define coresight_stm_reg(name, offset) \ coresight_simple_reg32(struct stm_drvdata, name, offset) @@ -819,14 +803,6 @@ static void stm_init_default_data(struct stm_drvdata *drvdata) */ drvdata->stmsper = ~0x0; - /* - * The trace ID value for *ETM* tracers start at CPU_ID * 2 + 0x10 and - * anything equal to or higher than 0x70 is reserved. Since 0x00 is - * also reserved the STM trace ID needs to be higher than 0x00 and - * lowner than 0x10. - */ - drvdata->traceid = 0x1; - /* Set invariant transaction timing on all channels */ bitmap_clear(drvdata->chs.guaranteed, 0, drvdata->numsp); } @@ -854,7 +830,7 @@ static void stm_init_generic_data(struct stm_drvdata *drvdata, static int stm_probe(struct amba_device *adev, const struct amba_id *id) { - int ret; + int ret, trace_id; void __iomem *base; struct device *dev = &adev->dev; struct coresight_platform_data *pdata = NULL; @@ -938,12 +914,22 @@ static int stm_probe(struct amba_device *adev, const struct amba_id *id) goto stm_unregister; } + trace_id = coresight_trace_id_get_system_id(); + if (trace_id < 0) { + ret = trace_id; + goto cs_unregister; + } + drvdata->traceid = (u8)trace_id; + pm_runtime_put(&adev->dev); dev_info(&drvdata->csdev->dev, "%s initialized\n", (char *)coresight_get_uci_data(id)); return 0; +cs_unregister: + coresight_unregister(drvdata->csdev); + stm_unregister: stm_unregister_device(&drvdata->stm); return ret; @@ -953,6 +939,7 @@ static void stm_remove(struct amba_device *adev) { struct stm_drvdata *drvdata = dev_get_drvdata(&adev->dev); + coresight_trace_id_put_system_id(drvdata->traceid); coresight_unregister(drvdata->csdev); stm_unregister_device(&drvdata->stm);