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Wed, 6 Jul 2022 18:34:53 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 6D2A9C341CD; Wed, 6 Jul 2022 18:34:53 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1657132493; bh=s0lSRIcjvOfwP4Cp805NU2rBzxJct6jJPyOlVilwJek=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=lB2PE5oG0KEqXmZem862TOYenNlWm816WPHd7CtPDidevAi4+2oJ9yXqF402Ybytb mnbc0ae6MRDtIZQG/2eO5GuB9D4Zb0xEZHvNMnX6I+yEoXB3TZxrgQFqKI52NmZWFk 3A/WUXBYnBex6jBftFB3nVDcJUvmS951/gDbJzDEiWozuY/254cZvyZPSvgs+W6lpN +gq3CtJB3exTaYTzPdTcUEKXji7VOCWypWwLZT4w93o6NufxQLcD3wpDfRzH+1KP+g GVnZIwo+cRDmXI4nU6dT0+5HYlI6CgPQIGbzMqmFvztxVecFPMz3v++cbVrbFeyudL MX05B8KG0YAmw== Received: by pali.im (Postfix) id 268A67BA; Wed, 6 Jul 2022 20:34:53 +0200 (CEST) From: =?utf-8?q?Pali_Roh=C3=A1r?= To: Andrew Lunn , Gregory Clement , Sebastian Hesselbarth , Rob Herring , =?utf-8?q?Marek_Beh=C3=BAn?= Cc: linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 08/11] ARM: dts: armada-375.dtsi: Add definitions for PCIe legacy INTx interrupts Date: Wed, 6 Jul 2022 20:31:11 +0200 Message-Id: <20220706183114.30783-9-pali@kernel.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20220706183114.30783-1-pali@kernel.org> References: <20220706183114.30783-1-pali@kernel.org> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220706_113454_436137_6158251D X-CRM114-Status: GOOD ( 12.32 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Signed-off-by: Pali Rohár --- arch/arm/boot/dts/armada-375.dtsi | 28 ++++++++++++++++++++++++---- 1 file changed, 24 insertions(+), 4 deletions(-) diff --git a/arch/arm/boot/dts/armada-375.dtsi b/arch/arm/boot/dts/armada-375.dtsi index 7f2f24a29e6c..929deaf312a5 100644 --- a/arch/arm/boot/dts/armada-375.dtsi +++ b/arch/arm/boot/dts/armada-375.dtsi @@ -568,16 +568,26 @@ reg = <0x0800 0 0 0 0>; #address-cells = <3>; #size-cells = <2>; + interrupt-names = "intx"; + interrupts-extended = <&gic GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; #interrupt-cells = <1>; ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0 0x81000000 0 0 0x81000000 0x1 0 1 0>; bus-range = <0x00 0xff>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &gic GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie0_intc 0>, + <0 0 0 2 &pcie0_intc 1>, + <0 0 0 3 &pcie0_intc 2>, + <0 0 0 4 &pcie0_intc 3>; marvell,pcie-port = <0>; marvell,pcie-lane = <0>; clocks = <&gateclk 5>; status = "disabled"; + + pcie0_intc: interrupt-controller { + interrupt-controller; + #interrupt-cells = <1>; + }; }; pcie1: pcie@2,0 { @@ -586,16 +596,26 @@ reg = <0x1000 0 0 0 0>; #address-cells = <3>; #size-cells = <2>; + interrupt-names = "intx"; + interrupts-extended = <&gic GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; #interrupt-cells = <1>; ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0 0x81000000 0 0 0x81000000 0x2 0 1 0>; bus-range = <0x00 0xff>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &gic GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie1_intc 0>, + <0 0 0 2 &pcie1_intc 1>, + <0 0 0 3 &pcie1_intc 2>, + <0 0 0 4 &pcie1_intc 3>; marvell,pcie-port = <0>; marvell,pcie-lane = <1>; clocks = <&gateclk 6>; status = "disabled"; + + pcie1_intc: interrupt-controller { + interrupt-controller; + #interrupt-cells = <1>; + }; }; };