From patchwork Tue Jul 12 16:41:07 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Marek_Beh=C3=BAn?= X-Patchwork-Id: 12915344 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id D5882C433EF for ; Tue, 12 Jul 2022 16:51:01 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=q25MQ8Cjq7ZcaWRBlHhTqUD5qRcBFZ0ZJ02Y7Y+nP3A=; b=lMd6JUjAmkD1SF nDSDi8lahG7lDLHO4/wqzdleHHMoBNp+VLXqQJamT/oaGsp4UjY6nlM2y/lrEtJQBp9g+p5tc36Jc 6aFdo4ebnBOO5EArHe4WL2IoKLObfU1ybyTCoBd5eIdIZ1/8Ms8+Va4nbZkMAEy19nYNR0tRhDiS6 L+gen7FZMCiHB1tNffnnRffmann81hg2Vfdpk3nI204AXeENXYH+OVmftyl1M8VIcMZ1+9L91ZVRP w1g33PokBn2YslqnGyJ+mw7thWlTNaQZZW+v30g+t7DUXZojJDNvRkvpj71vVbL+uO+L544MpCixi OsWrp8Xv+FWDRdGR8JKQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1oBJ52-00D0qi-T3; Tue, 12 Jul 2022 16:49:49 +0000 Received: from ams.source.kernel.org ([145.40.68.75]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1oBIx5-00CwBG-Kx for linux-arm-kernel@lists.infradead.org; Tue, 12 Jul 2022 16:41:37 +0000 Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ams.source.kernel.org (Postfix) with ESMTPS id 36324B81A76; Tue, 12 Jul 2022 16:41:34 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 1E5D6C3411E; Tue, 12 Jul 2022 16:41:30 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1657644092; bh=SXkMegj1u4GiyrfeNuHSsXbaYZEe6t2/pFH37yNDYX8=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=alu4x58Fz3PhWiB+Qs/MMSgBwvZNP1DIRwwl/7s/hODh69772NM1xvjLtC5Hq6c3R e1Cs2p2h744AXGJMoDtwThk7IGNkb8TxwpowQT+ZzT5EMlekaAna/GJB8z2S3kXqqW FGMSHvW2R8zTEjqFIKMXe2wvJ4mFWt87FKB+yjKkyoYb1zM//YHpttgjYdoOuu7ju+ 3egGfmlXUZDUtlg2Vmpv4EfsHu3IGTUekajyIYXsQp7tjquVmTXT45O7bH6PYNqYWA fb0O5DKYJCmu8iAo9T7MPSLyFggytEB7PTZMmg+xyDKHr8YvZbd1kDc8SsIrJFvch4 wzBfZjZBHXFrw== From: =?utf-8?q?Marek_Beh=C3=BAn?= To: Andrew Lunn , Gregory Clement , Sebastian Hesselbarth Cc: Rob Herring , =?utf-8?q?Pali_Roh=C3=A1r?= , linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, =?utf-8?q?Marek_Beh=C3=BAn?= Subject: [PATCH v2 09/10] ARM: dts: armada-380.dtsi: Add definitions for PCIe legacy INTx interrupts Date: Tue, 12 Jul 2022 18:41:07 +0200 Message-Id: <20220712164108.30262-10-kabel@kernel.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220712164108.30262-1-kabel@kernel.org> References: <20220712164108.30262-1-kabel@kernel.org> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220712_094136_049430_7765617A X-CRM114-Status: GOOD ( 14.58 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org From: Pali Rohár Add definitions for PCIe legacy INTx interrupts. This is required for example in a scenario where a driver requests only one of the legacy interrupts (INTA). Without this, the driver would be notified on events on all 4 (INTA, INTB, INTC, INTD), even if it requested only one of them. Signed-off-by: Pali Rohár Signed-off-by: Marek Behún --- arch/arm/boot/dts/armada-380.dtsi | 42 ++++++++++++++++++++++++++----- 1 file changed, 36 insertions(+), 6 deletions(-) diff --git a/arch/arm/boot/dts/armada-380.dtsi b/arch/arm/boot/dts/armada-380.dtsi index cff1269f3fbf..ce1dddb2269b 100644 --- a/arch/arm/boot/dts/armada-380.dtsi +++ b/arch/arm/boot/dts/armada-380.dtsi @@ -64,16 +64,26 @@ pcie@1,0 { reg = <0x0800 0 0 0 0>; #address-cells = <3>; #size-cells = <2>; + interrupt-names = "intx"; + interrupts-extended = <&gic GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; #interrupt-cells = <1>; ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0 0x81000000 0 0 0x81000000 0x1 0 1 0>; bus-range = <0x00 0xff>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &gic GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie1_intc 0>, + <0 0 0 2 &pcie1_intc 1>, + <0 0 0 3 &pcie1_intc 2>, + <0 0 0 4 &pcie1_intc 3>; marvell,pcie-port = <0>; marvell,pcie-lane = <0>; clocks = <&gateclk 8>; status = "disabled"; + + pcie1_intc: interrupt-controller { + interrupt-controller; + #interrupt-cells = <1>; + }; }; /* x1 port */ @@ -83,16 +93,26 @@ pcie@2,0 { reg = <0x1000 0 0 0 0>; #address-cells = <3>; #size-cells = <2>; + interrupt-names = "intx"; + interrupts-extended = <&gic GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; #interrupt-cells = <1>; ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0 0x81000000 0 0 0x81000000 0x2 0 1 0>; bus-range = <0x00 0xff>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &gic GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie2_intc 0>, + <0 0 0 2 &pcie2_intc 1>, + <0 0 0 3 &pcie2_intc 2>, + <0 0 0 4 &pcie2_intc 3>; marvell,pcie-port = <1>; marvell,pcie-lane = <0>; clocks = <&gateclk 5>; status = "disabled"; + + pcie2_intc: interrupt-controller { + interrupt-controller; + #interrupt-cells = <1>; + }; }; /* x1 port */ @@ -102,16 +122,26 @@ pcie@3,0 { reg = <0x1800 0 0 0 0>; #address-cells = <3>; #size-cells = <2>; + interrupt-names = "intx"; + interrupts-extended = <&gic GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; #interrupt-cells = <1>; ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0 0x81000000 0 0 0x81000000 0x3 0 1 0>; bus-range = <0x00 0xff>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &gic GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie3_intc 0>, + <0 0 0 2 &pcie3_intc 1>, + <0 0 0 3 &pcie3_intc 2>, + <0 0 0 4 &pcie3_intc 3>; marvell,pcie-port = <2>; marvell,pcie-lane = <0>; clocks = <&gateclk 6>; status = "disabled"; + + pcie3_intc: interrupt-controller { + interrupt-controller; + #interrupt-cells = <1>; + }; }; }; };