From patchwork Sun Jul 17 09:16:07 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tomer Maimon X-Patchwork-Id: 12920501 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 11DB0C43334 for ; Sun, 17 Jul 2022 09:21:46 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:CC:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=k1ukjIgjSlU7MOdb9YeOZDxeAH1AvizbAfGIyn+B2lQ=; b=f/Dm+yVV2eYcMt oAEXzv40Mr/WflrAMT8BesefIwKlHhfZyQdnrfJeAI5Z6vz9+mWGhl5bNVyvTZovABETHayhwGZZ2 khu1hS6DfR7YKZDfdO7ui+fvPqGttP9I66mQ9Pb7Bna7EBlk3IX5X2K86zRtVU+punJt6Gm1IaH4e XSDm+HOEgUQhuqJlCeRKbiY62Rzj+uXamx6B4iu0nicH+Un7OeQVBzMoSZI1HsqGc3g6H9seerLhw CuZI9mkptDLvM6S6a34ZIpmc6Tnhn1CFZYg+kI+4wRketEWDwtcSngX0Qru4IQ4l90TmOXJDtL48q klMygjMHn9k/XSR4TwMA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1oD0SB-0063tq-B0; Sun, 17 Jul 2022 09:20:44 +0000 Received: from maillog.nuvoton.com ([202.39.227.15]) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1oD0OC-0061tW-Hc for linux-arm-kernel@lists.infradead.org; Sun, 17 Jul 2022 09:16:40 +0000 Received: from NTHCCAS01.nuvoton.com (NTHCCAS01.nuvoton.com [10.1.8.28]) by maillog.nuvoton.com (Postfix) with ESMTP id 627291C811E9; Sun, 17 Jul 2022 17:16:28 +0800 (CST) Received: from NTHCCAS02.nuvoton.com (10.1.9.121) by NTHCCAS01.nuvoton.com (10.1.8.28) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.7; Sun, 17 Jul 2022 17:16:28 +0800 Received: from NTHCCAS01.nuvoton.com (10.1.8.28) by NTHCCAS02.nuvoton.com (10.1.9.121) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2176.2; Sun, 17 Jul 2022 17:16:27 +0800 Received: from taln60.nuvoton.co.il (10.191.1.180) by NTHCCAS01.nuvoton.com (10.1.12.25) with Microsoft SMTP Server id 15.1.2375.7 via Frontend Transport; Sun, 17 Jul 2022 17:16:27 +0800 Received: by taln60.nuvoton.co.il (Postfix, from userid 10070) id E5E5863A59; Sun, 17 Jul 2022 12:16:25 +0300 (IDT) From: Tomer Maimon To: , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , CC: , , , , , , Tomer Maimon , Krzysztof Kozlowski Subject: [PATCH v9 14/16] arm64: dts: nuvoton: Add initial NPCM8XX device tree Date: Sun, 17 Jul 2022 12:16:07 +0300 Message-ID: <20220717091609.122968-15-tmaimon77@gmail.com> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20220717091609.122968-1-tmaimon77@gmail.com> References: <20220717091609.122968-1-tmaimon77@gmail.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220717_021636_943536_E9D2ADD5 X-CRM114-Status: GOOD ( 11.25 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org This adds initial device tree support for the Nuvoton NPCM845 Board Management controller (BMC) SoC family. The NPCM845 based quad-core Cortex-A35 ARMv8 architecture and have various peripheral IPs. Signed-off-by: Tomer Maimon Reviewed-by: Krzysztof Kozlowski --- arch/arm64/boot/dts/Makefile | 1 + .../dts/nuvoton/nuvoton-common-npcm8xx.dtsi | 170 ++++++++++++++++++ .../boot/dts/nuvoton/nuvoton-npcm845.dtsi | 76 ++++++++ 3 files changed, 247 insertions(+) create mode 100644 arch/arm64/boot/dts/nuvoton/nuvoton-common-npcm8xx.dtsi create mode 100644 arch/arm64/boot/dts/nuvoton/nuvoton-npcm845.dtsi diff --git a/arch/arm64/boot/dts/Makefile b/arch/arm64/boot/dts/Makefile index 1ba04e31a438..7b107fa7414b 100644 --- a/arch/arm64/boot/dts/Makefile +++ b/arch/arm64/boot/dts/Makefile @@ -19,6 +19,7 @@ subdir-y += lg subdir-y += marvell subdir-y += mediatek subdir-y += microchip +subdir-y += nuvoton subdir-y += nvidia subdir-y += qcom subdir-y += realtek diff --git a/arch/arm64/boot/dts/nuvoton/nuvoton-common-npcm8xx.dtsi b/arch/arm64/boot/dts/nuvoton/nuvoton-common-npcm8xx.dtsi new file mode 100644 index 000000000000..aa7aac8c3774 --- /dev/null +++ b/arch/arm64/boot/dts/nuvoton/nuvoton-common-npcm8xx.dtsi @@ -0,0 +1,170 @@ +// SPDX-License-Identifier: GPL-2.0 +// Copyright (c) 2021 Nuvoton Technology tomer.maimon@nuvoton.com + +#include +#include +#include + +/ { + #address-cells = <2>; + #size-cells = <2>; + interrupt-parent = <&gic>; + + soc { + #address-cells = <2>; + #size-cells = <2>; + compatible = "simple-bus"; + interrupt-parent = <&gic>; + ranges; + + gcr: system-controller@f0800000 { + compatible = "nuvoton,npcm845-gcr", "syscon"; + reg = <0x0 0xf0800000 0x0 0x1000>; + }; + + gic: interrupt-controller@dfff9000 { + compatible = "arm,gic-400"; + reg = <0x0 0xdfff9000 0x0 0x1000>, + <0x0 0xdfffa000 0x0 0x2000>, + <0x0 0xdfffc000 0x0 0x2000>, + <0x0 0xdfffe000 0x0 0x2000>; + interrupts = ; + #interrupt-cells = <3>; + interrupt-controller; + #address-cells = <0>; + ppi-partitions { + ppi_cluster0: interrupt-partition-0 { + affinity = <&cpu0 &cpu1 &cpu2 &cpu3>; + }; + }; + }; + }; + + ahb { + #address-cells = <2>; + #size-cells = <2>; + compatible = "simple-bus"; + interrupt-parent = <&gic>; + ranges; + + rstc: reset-controller@f0801000 { + compatible = "nuvoton,npcm845-reset"; + reg = <0x0 0xf0801000 0x0 0x78>; + #reset-cells = <2>; + nuvoton,sysgcr = <&gcr>; + }; + + clk: clock-controller@f0801000 { + compatible = "nuvoton,npcm845-clk"; + #clock-cells = <1>; + reg = <0x0 0xf0801000 0x0 0x1000>; + }; + + apb { + #address-cells = <1>; + #size-cells = <1>; + compatible = "simple-bus"; + interrupt-parent = <&gic>; + ranges = <0x0 0x0 0xf0000000 0x00300000>, + <0xfff00000 0x0 0xfff00000 0x00016000>; + + timer0: timer@8000 { + compatible = "nuvoton,npcm845-timer"; + interrupts = ; + reg = <0x8000 0x1C>; + clocks = <&clk NPCM8XX_CLK_REFCLK>; + clock-names = "refclk"; + }; + + serial0: serial@0 { + compatible = "nuvoton,npcm845-uart", "nuvoton,npcm750-uart"; + reg = <0x0 0x1000>; + clocks = <&clk NPCM8XX_CLK_UART>; + interrupts = ; + reg-shift = <2>; + status = "disabled"; + }; + + serial1: serial@1000 { + compatible = "nuvoton,npcm845-uart", "nuvoton,npcm750-uart"; + reg = <0x1000 0x1000>; + clocks = <&clk NPCM8XX_CLK_UART>; + interrupts = ; + reg-shift = <2>; + status = "disabled"; + }; + + serial2: serial@2000 { + compatible = "nuvoton,npcm845-uart", "nuvoton,npcm750-uart"; + reg = <0x2000 0x1000>; + clocks = <&clk NPCM8XX_CLK_UART>; + interrupts = ; + reg-shift = <2>; + status = "disabled"; + }; + + serial3: serial@3000 { + compatible = "nuvoton,npcm845-uart", "nuvoton,npcm750-uart"; + reg = <0x3000 0x1000>; + clocks = <&clk NPCM8XX_CLK_UART>; + interrupts = ; + reg-shift = <2>; + status = "disabled"; + }; + + serial4: serial@4000 { + compatible = "nuvoton,npcm845-uart", "nuvoton,npcm750-uart"; + reg = <0x4000 0x1000>; + clocks = <&clk NPCM8XX_CLK_UART>; + interrupts = ; + reg-shift = <2>; + status = "disabled"; + }; + + serial5: serial@5000 { + compatible = "nuvoton,npcm845-uart", "nuvoton,npcm750-uart"; + reg = <0x5000 0x1000>; + clocks = <&clk NPCM8XX_CLK_UART>; + interrupts = ; + reg-shift = <2>; + status = "disabled"; + }; + + serial6: serial@6000 { + compatible = "nuvoton,npcm845-uart", "nuvoton,npcm750-uart"; + reg = <0x6000 0x1000>; + clocks = <&clk NPCM8XX_CLK_UART>; + interrupts = ; + reg-shift = <2>; + status = "disabled"; + }; + + watchdog0: watchdog@801c { + compatible = "nuvoton,npcm845-wdt", "nuvoton,npcm750-wdt"; + interrupts = ; + reg = <0x801c 0x4>; + status = "disabled"; + clocks = <&clk NPCM8XX_CLK_REFCLK>; + syscon = <&gcr>; + }; + + watchdog1: watchdog@901c { + compatible = "nuvoton,npcm845-wdt", "nuvoton,npcm750-wdt"; + interrupts = ; + reg = <0x901c 0x4>; + status = "disabled"; + clocks = <&clk NPCM8XX_CLK_REFCLK>; + syscon = <&gcr>; + }; + + watchdog2: watchdog@a01c { + compatible = "nuvoton,npcm845-wdt", "nuvoton,npcm750-wdt"; + interrupts = ; + reg = <0xa01c 0x4>; + status = "disabled"; + clocks = <&clk NPCM8XX_CLK_REFCLK>; + syscon = <&gcr>; + }; + }; + }; +}; diff --git a/arch/arm64/boot/dts/nuvoton/nuvoton-npcm845.dtsi b/arch/arm64/boot/dts/nuvoton/nuvoton-npcm845.dtsi new file mode 100644 index 000000000000..12118b75c0e6 --- /dev/null +++ b/arch/arm64/boot/dts/nuvoton/nuvoton-npcm845.dtsi @@ -0,0 +1,76 @@ +// SPDX-License-Identifier: GPL-2.0 +// Copyright (c) 2021 Nuvoton Technology tomer.maimon@nuvoton.com + +#include "nuvoton-common-npcm8xx.dtsi" + +/ { + #address-cells = <2>; + #size-cells = <2>; + + cpus { + #address-cells = <2>; + #size-cells = <0>; + + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a35"; + clocks = <&clk NPCM8XX_CLK_CPU>; + reg = <0x0 0x0>; + next-level-cache = <&l2>; + enable-method = "psci"; + }; + + cpu1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a35"; + clocks = <&clk NPCM8XX_CLK_CPU>; + reg = <0x0 0x1>; + next-level-cache = <&l2>; + enable-method = "psci"; + }; + + cpu2: cpu@2 { + device_type = "cpu"; + compatible = "arm,cortex-a35"; + clocks = <&clk NPCM8XX_CLK_CPU>; + reg = <0x0 0x2>; + next-level-cache = <&l2>; + enable-method = "psci"; + }; + + cpu3: cpu@3 { + device_type = "cpu"; + compatible = "arm,cortex-a35"; + clocks = <&clk NPCM8XX_CLK_CPU>; + reg = <0x0 0x3>; + next-level-cache = <&l2>; + enable-method = "psci"; + }; + + l2: l2-cache { + compatible = "cache"; + }; + }; + + arm-pmu { + compatible = "arm,cortex-a35-pmu"; + interrupts = , + , + , + ; + interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; + }; + + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = , + , + , + ; + }; +};