| Message ID | 20220727125610.20782-1-kabel@kernel.org (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | [mvebu-dt] ARM: dts: turris-omnia: Fix mpp26 pin name and comment | expand |
Marek Behún <kabel@kernel.org> writes: > There is a bug in Turris Omnia's schematics, whereupon the MPP[26] pin, > which is routed to CN11 pin header, is documented as SPI CS1, but > MPP[26] pin does not support this function. Instead it controls chip > select 2 if in "spi0" mode. > > Fix the name of the pin node in pinctrl node and fix the comment in SPI > node. > > Fixes: 26ca8b52d6e1 ("ARM: dts: add support for Turris Omnia") > Signed-off-by: Marek Behún <kabel@kernel.org> Applied on mvebu/dt Thanks, Gregory > --- > arch/arm/boot/dts/armada-385-turris-omnia.dts | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git a/arch/arm/boot/dts/armada-385-turris-omnia.dts b/arch/arm/boot/dts/armada-385-turris-omnia.dts > index f4878df39753..487dece2033c 100644 > --- a/arch/arm/boot/dts/armada-385-turris-omnia.dts > +++ b/arch/arm/boot/dts/armada-385-turris-omnia.dts > @@ -478,7 +478,7 @@ spi0cs0_pins: spi0cs0-pins { > marvell,function = "spi0"; > }; > > - spi0cs1_pins: spi0cs1-pins { > + spi0cs2_pins: spi0cs2-pins { > marvell,pins = "mpp26"; > marvell,function = "spi0"; > }; > @@ -513,7 +513,7 @@ partition@100000 { > }; > }; > > - /* MISO, MOSI, SCLK and CS1 are routed to pin header CN11 */ > + /* MISO, MOSI, SCLK and CS2 are routed to pin header CN11 */ > }; > > &uart0 { > -- > 2.35.1 >
diff --git a/arch/arm/boot/dts/armada-385-turris-omnia.dts b/arch/arm/boot/dts/armada-385-turris-omnia.dts index f4878df39753..487dece2033c 100644 --- a/arch/arm/boot/dts/armada-385-turris-omnia.dts +++ b/arch/arm/boot/dts/armada-385-turris-omnia.dts @@ -478,7 +478,7 @@ spi0cs0_pins: spi0cs0-pins { marvell,function = "spi0"; }; - spi0cs1_pins: spi0cs1-pins { + spi0cs2_pins: spi0cs2-pins { marvell,pins = "mpp26"; marvell,function = "spi0"; }; @@ -513,7 +513,7 @@ partition@100000 { }; }; - /* MISO, MOSI, SCLK and CS1 are routed to pin header CN11 */ + /* MISO, MOSI, SCLK and CS2 are routed to pin header CN11 */ }; &uart0 {
There is a bug in Turris Omnia's schematics, whereupon the MPP[26] pin, which is routed to CN11 pin header, is documented as SPI CS1, but MPP[26] pin does not support this function. Instead it controls chip select 2 if in "spi0" mode. Fix the name of the pin node in pinctrl node and fix the comment in SPI node. Fixes: 26ca8b52d6e1 ("ARM: dts: add support for Turris Omnia") Signed-off-by: Marek Behún <kabel@kernel.org> --- arch/arm/boot/dts/armada-385-turris-omnia.dts | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)