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[3/3] ARM: dts: bcmbca: bcm6846: fix interrupt controller node

Message ID 20220801194647.29437-3-william.zhang@broadcom.com (mailing list archive)
State New, archived
Headers show
Series [1/3] ARM: dts: bcmbca: bcm6846: fix timer node cpu mask flag | expand

Commit Message

William Zhang Aug. 1, 2022, 7:46 p.m. UTC
Add the missing gic registers and interrupts property to the gic node.

Fixes: de1a99ac0b64 ("ARM: dts: Add DTS files for bcmbca SoC BCM6846")
Signed-off-by: William Zhang <william.zhang@broadcom.com>

---

 arch/arm/boot/dts/bcm6846.dtsi | 8 +++++---
 1 file changed, 5 insertions(+), 3 deletions(-)

Comments

Florian Fainelli Aug. 4, 2022, 6:07 p.m. UTC | #1
On Mon,  1 Aug 2022 12:46:47 -0700, William Zhang <william.zhang@broadcom.com> wrote:
> Add the missing gic registers and interrupts property to the gic node.
> 
> Fixes: de1a99ac0b64 ("ARM: dts: Add DTS files for bcmbca SoC BCM6846")
> Signed-off-by: William Zhang <william.zhang@broadcom.com>
> 
> ---

Applied to https://github.com/Broadcom/stblinux/commits/devicetree/fixes, thanks!
--
Florian
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Patch

diff --git a/arch/arm/boot/dts/bcm6846.dtsi b/arch/arm/boot/dts/bcm6846.dtsi
index 9876ceb1d47c..8aa47a2583b2 100644
--- a/arch/arm/boot/dts/bcm6846.dtsi
+++ b/arch/arm/boot/dts/bcm6846.dtsi
@@ -71,15 +71,17 @@  axi@81000000 {
 		compatible = "simple-bus";
 		#address-cells = <1>;
 		#size-cells = <1>;
-		ranges = <0 0x81000000 0x4000>;
+		ranges = <0 0x81000000 0x8000>;
 
 		gic: interrupt-controller@1000 {
 			compatible = "arm,cortex-a7-gic";
 			#interrupt-cells = <3>;
-			#address-cells = <0>;
 			interrupt-controller;
+			interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
 			reg = <0x1000 0x1000>,
-				<0x2000 0x2000>;
+				<0x2000 0x2000>,
+				<0x4000 0x2000>,
+				<0x6000 0x2000>;
 		};
 	};