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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: KuOyzh8e9MVYcXbDY/VM8e1doXV5oSjj15pBxpfegmA6Qyj/Y8PmXDx8nZPWK3BXrPujvzbqnfk5zXNwMC18ZIauEpEvqkunlBt8F/6F70+HkJIHIEyq3vGCfE0cjLX/2Ice/6240T7GvHcjhCN9hkADu0vzZc12jK8PzNBfszAefH95hcGkxYP+yfldRV+MeOXx7vwOAy/FvRUT9NBDc+TIXaPLBvghTPImUNR8kUdznU92MgtkGjtMooBw/TXhDGrbr43Ibc2jrRAKVS321vnSKZZXY1LbwfLX6aVFzI1JpOXSrbc1hkU7zGlEcfL4bpDZieGD0tWmfDTHoh8YeQjCMXroEd+OxNI1jyDJalBDdWvi100ZQtqctIY+KH+3QB06zjUQUXc4yj10T6/KIEFvSy2KtA4oj+TfO7TN/OWBNsh1wXm+9G6MfJmMK1BL/WIeCUQ9LQH8b6Sr13cP2Hlj2qb9Hb7YWONOq8qiWTQRthREzJJLwVseutQXlsQSmFM5FmyufhqtNPL60mU6ktkh4BUY9Z15mOd3hZVAk5p1MrMFAhk/SdFMsHquwaJwejx3G6wyEepG8AJ7bGrsSRqjG0r+tJoKG6QaGbobB5Q5vkNJPU6u30D/6DEeUv5FeI2qzdTyHAzYMqAPvm5wqHmYsdDDo+BeTK2LD9adumDChRNm573eiYJhQ7caEDQPr+TzfdymcIt/G/dd5XZVRoADLk0piDAT8u4Qf8DnZY0M4n+HDFG3lfIHukzYrQx0tuhYsZtvpwvY7pwUjLwbrpho+uQDjcttL1rlfW4i3Pxxpxot6vq5luQBXm9GTIPV8aSBXCf4P04qDY+1XUnWnGRi6PqWjhEedeumXGB9gd4LW2F7eJ2s+zZB0lD2VoIVE/swoMVK5VBoNnmbMlXJXZf0vx1LMK7t6LZMtBpDrzR/T73WKGD4lIxYtQ3V5zuEU+wRQEOO64SEJqqgZnOeejtp/L4o4Mn8Cm3sCPK9puDWbmxrbLdXUI090AE5ExJSXS27qLh5/3OSi0yt4TRtpwAgT3/ofIotNzhCzJvrgVstZzyiTZaJDI0/NJaLAayl3BZlYL9OGTHHob8WAtBMBjt1e9YzeEdk66pD3UcvptvuVgWylZpaOqz5wQG0ZdmhoXI0/zctorRpxt+cl6hHI28CatRjA25cjCeuM8rgN0qn83fa5aZ+GMnnMHdMuF9wPiYKqLifBzxqomJFJLffR+dJnYMxfsmQutm7Pg9aw8BgW68HH+fptRbjHsr7N5GadQtQVow1yiQAOir5YkloSgAvFQg05IFx8y7e25cnL/88o05uSTSU3jLMzOd0R+Ypr4ZzvutLJxPPuBaCvOKN6leI4fUBem9rGkEowYjU7CahVdZjdfWQZFMEnTISEtTv3vcLYpPNHdFmBUrQobC8Vmib7MSPcUSMxtq7O6LTZjEG7W/dsESP7SGX+uszHJgFVnzd0ERjMDucYGILgYtTkv7OPvzmt13KbkqZBxe1/uT+brCjElPO2aQfE8jyE83UxZ47ZztFY0iQGp2ntmbBb72pzuS5Tc4onAyvA9q3yCLy2iWlt3dXYz6QGSTVFNY1 X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: 3912b1fb-c19b-40d4-4091-08da75dffd4d X-MS-Exchange-CrossTenant-AuthSource: AM7PR04MB7046.eurprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 04 Aug 2022 06:10:11.5763 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: ptahw9Xv3CIibqpRjIsNYbzuF9KbljqH/H5K7Ylmmsv0t/DillUnCjnJTUwKrMy34aa2RlFba2Kh54dGt9CMeQ== X-MS-Exchange-Transport-CrossTenantHeadersStamped: DBBPR04MB7721 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220803_231014_943557_4A7E6280 X-CRM114-Status: GOOD ( 18.90 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Freescale i.MX8qxp pixel link MSI bus is a simple memory-mapped bus. It is used to access peripherals in i.MX8qm/qxp imaging, LVDS, MIPI DSI and HDMI TX subsystems, like I2C controller, PWM controller, MIPI DSI controller and Control and Status Registers (CSR) module. Reference simple-pm-bus bindings and add Freescale i.MX8qxp pixel link MSI bus specific bindings. Signed-off-by: Liu Ying --- v2->v3: * Add a pattern property to allow child nodes. (Rob) v1->v2: Address Krzysztof's comments: * Add a select to explicitly select the MSI bus dt-binding. * List 'simple-pm-bus' explicitly as one item of compatible strings. * Require compatible and reg properties. * Put reg property just after compatible property in example. .../bus/fsl,imx8qxp-pixel-link-msi-bus.yaml | 108 ++++++++++++++++++ 1 file changed, 108 insertions(+) create mode 100644 Documentation/devicetree/bindings/bus/fsl,imx8qxp-pixel-link-msi-bus.yaml diff --git a/Documentation/devicetree/bindings/bus/fsl,imx8qxp-pixel-link-msi-bus.yaml b/Documentation/devicetree/bindings/bus/fsl,imx8qxp-pixel-link-msi-bus.yaml new file mode 100644 index 000000000000..9fc6623a7061 --- /dev/null +++ b/Documentation/devicetree/bindings/bus/fsl,imx8qxp-pixel-link-msi-bus.yaml @@ -0,0 +1,108 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/bus/fsl,imx8qxp-pixel-link-msi-bus.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Freescale i.MX8qxp Pixel Link Medium Speed Interconnect (MSI) Bus + +maintainers: + - Liu Ying + +description: | + i.MX8qxp pixel link MSI bus is used to control settings of PHYs, I/Os + sitting together with the PHYs. It is not the same as the MSI bus coming + from i.MX8 System Controller Unit (SCU) which is used to control power, + clock and reset through the i.MX8 Distributed Slave System Controller (DSC). + + i.MX8qxp pixel link MSI bus is a simple memory-mapped bus. Two input clocks, + that is, MSI clock and AHB clock, need to be enabled so that peripherals + connected to the bus can be accessed. Also, the bus is part of a power + domain. The power domain needs to be enabled before the peripherals can + be accessed. + + Peripherals in i.MX8qm/qxp imaging, LVDS, MIPI DSI and HDMI TX subsystems, + like I2C controller, PWM controller, MIPI DSI controller and Control and + Status Registers (CSR) module, are accessed through the bus. + + The i.MX System Controller Firmware (SCFW) owns and uses the i.MX8qm/qxp + pixel link MSI bus controller and does not allow SCFW user to control it. + So, the controller's registers cannot be accessed by SCFW user. Hence, + the interrupts generated by the controller don't make any sense from SCFW + user's point of view. + +allOf: + - $ref: simple-pm-bus.yaml# + +# We need a select here so we don't match all nodes with 'simple-pm-bus'. +select: + properties: + compatible: + contains: + enum: + - fsl,imx8qxp-display-pixel-link-msi-bus + - fsl,imx8qm-display-pixel-link-msi-bus + required: + - compatible + +properties: + compatible: + items: + - enum: + - fsl,imx8qxp-display-pixel-link-msi-bus + - fsl,imx8qm-display-pixel-link-msi-bus + - const: simple-pm-bus + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + items: + - description: master gated clock from system + - description: AHB clock + + clock-names: + items: + - const: msi + - const: ahb + +patternProperties: + "^.*@[0-9a-f]+$": + description: Devices attached to the bus + type: object + properties: + reg: + maxItems: 1 + + required: + - reg + +required: + - compatible + - reg + - clocks + - clock-names + - power-domains + +unevaluatedProperties: false + +examples: + - | + #include + #include + bus@56200000 { + compatible = "fsl,imx8qxp-display-pixel-link-msi-bus", "simple-pm-bus"; + reg = <0x56200000 0x20000>; + #address-cells = <1>; + #size-cells = <1>; + interrupt-parent = <&dc0_irqsteer>; + interrupts = <320>; + ranges; + clocks = <&dc0_disp_ctrl_link_mst0_lpcg IMX_LPCG_CLK_4>, + <&dc0_disp_ctrl_link_mst0_lpcg IMX_LPCG_CLK_4>; + clock-names = "msi", "ahb"; + power-domains = <&pd IMX_SC_R_DC_0>; + };