From patchwork Fri Aug 5 12:22:00 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Pali_Roh=C3=A1r?= X-Patchwork-Id: 12937246 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 50A5EC00140 for ; Fri, 5 Aug 2022 12:27:15 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=GM0kB03lmHHguUi6l+h30nstHbJU/XDwp3U3fvMevLA=; b=186cqnB2fQk0lp iHA84V9a3j5Erqp76TkoIpQ+eg2R/34LTVdYub+DvJW79AcYdojw47udgA/d+/dGEL/T2aM+iRI8k 10n+c3/yPhivLMstnDqHsAVRFXG3w5fstDmExDDf2ZxhyVbKxz2WcdRu+wHUP1aWDEpw7R/l/bDKM iycvHlMxPNqxgpLbIfnnx0b2KZANnScmjPmeGtbDaHSlI6IyI1h1IAsR3N9QIdtwrme5IRvR49CU4 qWWhJ3n6yHNPjd9o5zd84+5Qg8n7gWnjtNKJy6Mip+9n65g6ryoZ+8rzIgkyzqSqoHjNfDJIyrrV/ 0I8uBgPApcCMMfKKavRg==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1oJwOy-00Esrn-Ta; Fri, 05 Aug 2022 12:26:05 +0000 Received: from sin.source.kernel.org ([145.40.73.55]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1oJwLW-00EqZj-62 for linux-arm-kernel@lists.infradead.org; Fri, 05 Aug 2022 12:22:31 +0000 Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by sin.source.kernel.org (Postfix) with ESMTPS id ABE36CE28C5; Fri, 5 Aug 2022 12:22:23 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id EE384C4347C; Fri, 5 Aug 2022 12:22:21 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1659702142; bh=b9e6f7QyGeXEQipqkQe1Q41JGjIlUd+dl7sHDQm0Ydk=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=AL//8Tj3FjVfZYalJJP/aVwVEmAdJouVah4hhxuD+9x2XaPW75jr1jPZdMjANUZIr Pa502tpQZJDZJqpHihD4hUnV/XHhVy+39rtoEyLEBuDxSGXbShnaxyr74R0RopwX7A wKHwvFlwWcxdnk7hrH8m6IpPqACgvjsAlCpmwtwWj/CXcGmCHXOoIVrJTga686a05b nd4dlCmEniIIABRvirNOcfOY8iPjMFqYbZjJI3cja6Jjq10lA2yEMJUs8D+Oyod64z ZVwcgNZvhrMkqEeuKQwHLvqUISRiK2aUkvL5Na/9hR3TR37NfKodJ2PiDAc28j7WEO r4FVOUvvj0caw== Received: by pali.im (Postfix) id 6D972941; Fri, 5 Aug 2022 14:22:19 +0200 (CEST) From: =?utf-8?q?Pali_Roh=C3=A1r?= To: Andrew Lunn , Gregory Clement , Sebastian Hesselbarth , Linus Walleij Cc: =?utf-8?q?Marek_Beh=C3=BAn?= , linux-arm-kernel@lists.infradead.org, linux-gpio@vger.kernel.org Subject: [PATCH v2 2/4] pinctrl: armada-37xx: Fix definitions for MPP pins 20-22 Date: Fri, 5 Aug 2022 14:22:00 +0200 Message-Id: <20220805122202.23174-2-pali@kernel.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20220805122202.23174-1-pali@kernel.org> References: <20220805122202.23174-1-pali@kernel.org> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220805_052230_439229_F531A317 X-CRM114-Status: GOOD ( 13.34 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org All 3 MPP pins (20, 21 and 22) can be configured individually and also can be configured to GPIO functions. Fix definitions for these MPP pins in existing pin groups. After this change GPIO function can be enabled just for one of these 3 pins. Fixes: 87466ccd9401 ("pinctrl: armada-37xx: Add pin controller support for Armada 37xx") Signed-off-by: Pali Rohár Reviewed-by: Andrew Lunn --- drivers/pinctrl/mvebu/pinctrl-armada-37xx.c | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/drivers/pinctrl/mvebu/pinctrl-armada-37xx.c b/drivers/pinctrl/mvebu/pinctrl-armada-37xx.c index 2b44c634ccb5..e5e5f0ea0e77 100644 --- a/drivers/pinctrl/mvebu/pinctrl-armada-37xx.c +++ b/drivers/pinctrl/mvebu/pinctrl-armada-37xx.c @@ -213,9 +213,11 @@ static struct armada_37xx_pin_group armada_37xx_sb_groups[] = { PIN_GRP_GPIO("pcie1", 3, 1, BIT(5), "pcie"), /* this actually controls "pcie1_reset" */ PIN_GRP_GPIO("pcie1_clkreq", 4, 1, BIT(9), "pcie"), PIN_GRP_GPIO("pcie1_wakeup", 5, 1, BIT(10), "pcie"), - PIN_GRP_GPIO("ptp", 20, 3, BIT(11) | BIT(12) | BIT(13), "ptp"), - PIN_GRP("ptp_clk", 21, 1, BIT(6), "ptp", "mii"), - PIN_GRP("ptp_trig", 22, 1, BIT(7), "ptp", "mii"), + PIN_GRP_GPIO("ptp", 20, 1, BIT(11), "ptp"), + PIN_GRP_GPIO_3("ptp_clk", 21, 1, BIT(6) | BIT(12), 0, BIT(6), BIT(12), + "ptp", "mii"), + PIN_GRP_GPIO_3("ptp_trig", 22, 1, BIT(7) | BIT(13), 0, BIT(7), BIT(13), + "ptp", "mii"), PIN_GRP_GPIO_3("mii_col", 23, 1, BIT(8) | BIT(14), 0, BIT(8), BIT(14), "mii", "mii_err"), };