From patchwork Tue Aug 9 22:33:51 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mike Leach X-Patchwork-Id: 12940037 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id C2977C25B08 for ; Tue, 9 Aug 2022 22:35:53 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:MIME-Version:List-Subscribe:List-Help: List-Post:List-Archive:List-Unsubscribe:List-Id:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=u9+uTx+hSEFrEfe47gNu2lVDuCoqMPeaZGmu/5uReXg=; b=xl02/QU7d4pSPt /pGti16ugotXozaznls+PbwLXz9f4Ei424MWKHq4LXDDEpFMsUoAJMkX/QewSt1OMNXs/7eMlFHiu 3FUYa+R5xRzCCH3Ax8zQ/KZFtaGvD9itK90eZv87Dlwj/6Fu9mFdrHhFsJSYqPz8Sd5YTwUL9mpda slhdfSEFYDjZiw0ksl+dHl2h6VzoQJlnFfQ92g91lZyzRZWnNlvmAeAQQDcOwCy9lKN/UxHe/XVHW p4JWZzt5K/xA/Fb+vv8f5QO6rvbv57rhfGNzfukadWz2xV6yaIrsSDYy9cZOY+VW4KP2Ffm19wOq/ sWEdiyUJe1r3v3ByiGLw==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1oLXoF-0073jL-8l; Tue, 09 Aug 2022 22:34:47 +0000 Received: from mail-wr1-x42f.google.com ([2a00:1450:4864:20::42f]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1oLXnf-0073VF-U9 for linux-arm-kernel@lists.infradead.org; Tue, 09 Aug 2022 22:34:16 +0000 Received: by mail-wr1-x42f.google.com with SMTP id v3so15896507wrp.0 for ; Tue, 09 Aug 2022 15:34:10 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=pwmExfB0GU/JJ9bsvT+Z4EqrCVu9SNKAksEtRHBxI8c=; b=Z4RIHXx2IQwAP86ikkh4MNKsWkkqKaqtVe7+XWls9mfoBm1XVBXKdaxnV0rAABxB8F zzAOptbOaCD2N+sPvVv/Us4uZbDH4QaTw3cVStW72TdA5ctoG79RDmDsV8qN54MoDElW NegpbPFuGJtw2irpEOxr6Dagjq1WShiAq3+JXY7ptTSaYOzqyMxvh6ZrcXdWIrtEykx1 mwrGeeXpxlXv+sXubgNompPOSzBNah47Mz3ZIQedtfOTkiyON5vLZVkDAXmjYyre912V IWjUMEyrBQDoO7tPym7/m44GSqXZkGBqgwuR6iL3+c0I9+qYLVv5dhZfVbKkNzqvyVkE SU0A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=pwmExfB0GU/JJ9bsvT+Z4EqrCVu9SNKAksEtRHBxI8c=; b=SbqvK9XC7zTFsl2FOuX7otpoDzD53a33CG1KFL8LvuLHmyths8GbMtW9WLrERcu0+9 r3Ezr10hEv6GT0SA8MKD7qNA9N2T3oCIC2BRMwyDW0tRi6sHTwWuk5QB7DKb6h0HL9Ic 79cjGaWqDKxpDohQUW+HO0rTwQBwcpBkLKLlLEh3RSI/C4vZ11/Vwx1wjuYf2ac0Zn6q AhK8Yf9TCs8LLECLMnDvkx1Tf0yTOXWGzT7VTWKtreCwHD9rx+qiyqCAgC6YmxOjvcKj dZpFl3bArmHG30r/o0nrbK3zaZRBGIVkS68ZrZk4bobXEfCHXZGaXLouNAIxd2YGeple 7t1w== X-Gm-Message-State: ACgBeo22l/fVy1+9sH6Qiho0NTl9pNr4B+5B/NP6REyDPXinnRqQewrC NX7F94xJ69ZhOXh5m2notTeoSw== X-Google-Smtp-Source: AA6agR7EUmPacdCEPnPG02meijZWkKgpofbAikoxKS59mwKYjzne7lsFcnucKSh9I9HHbzWw+zAZUw== X-Received: by 2002:adf:fd0d:0:b0:21e:f27b:10dd with SMTP id e13-20020adffd0d000000b0021ef27b10ddmr16064160wrr.295.1660084449201; Tue, 09 Aug 2022 15:34:09 -0700 (PDT) Received: from linaro.org ([2a00:23c5:6809:2201:a6:74a6:5a0e:f3e2]) by smtp.gmail.com with ESMTPSA id e20-20020a05600c4b9400b003a2cf1ba9e2sm311650wmp.6.2022.08.09.15.34.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 09 Aug 2022 15:34:08 -0700 (PDT) From: Mike Leach To: coresight@lists.linaro.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Cc: mathieu.poirier@linaro.org, suzuki.poulose@arm.com, peterz@infradead.org, mingo@redhat.com, acme@kernel.org, linux-perf-users@vger.kernel.org, leo.yan@linaro.org, quic_jinlmao@quicinc.com, Mike Leach Subject: [PATCH v3 03/13] coresight: stm: Update STM driver to use Trace ID API Date: Tue, 9 Aug 2022 23:33:51 +0100 Message-Id: <20220809223401.24599-4-mike.leach@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20220809223401.24599-1-mike.leach@linaro.org> References: <20220809223401.24599-1-mike.leach@linaro.org> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220809_153411_994891_6432A00A X-CRM114-Status: GOOD ( 21.02 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Updates the STM driver to use the trace ID allocation API. This uses the _system_id calls to allocate an ID on device poll, and release on device remove. The sysfs access to the STMTRACEIDR register has been changed from RW to RO. Having this value as writable is not appropriate for the new Trace ID scheme - and had potential to cause errors in the previous scheme if values clashed with other sources. Signed-off-by: Mike Leach Reviewed-by: Suzuki K Poulose --- drivers/hwtracing/coresight/coresight-stm.c | 41 +++++++-------------- 1 file changed, 14 insertions(+), 27 deletions(-) diff --git a/drivers/hwtracing/coresight/coresight-stm.c b/drivers/hwtracing/coresight/coresight-stm.c index bb14a3a8a921..9ef3e923a930 100644 --- a/drivers/hwtracing/coresight/coresight-stm.c +++ b/drivers/hwtracing/coresight/coresight-stm.c @@ -31,6 +31,7 @@ #include #include "coresight-priv.h" +#include "coresight-trace-id.h" #define STMDMASTARTR 0xc04 #define STMDMASTOPR 0xc08 @@ -615,24 +616,7 @@ static ssize_t traceid_show(struct device *dev, val = drvdata->traceid; return sprintf(buf, "%#lx\n", val); } - -static ssize_t traceid_store(struct device *dev, - struct device_attribute *attr, - const char *buf, size_t size) -{ - int ret; - unsigned long val; - struct stm_drvdata *drvdata = dev_get_drvdata(dev->parent); - - ret = kstrtoul(buf, 16, &val); - if (ret) - return ret; - - /* traceid field is 7bit wide on STM32 */ - drvdata->traceid = val & 0x7f; - return size; -} -static DEVICE_ATTR_RW(traceid); +static DEVICE_ATTR_RO(traceid); #define coresight_stm_reg(name, offset) \ coresight_simple_reg32(struct stm_drvdata, name, offset) @@ -819,14 +803,6 @@ static void stm_init_default_data(struct stm_drvdata *drvdata) */ drvdata->stmsper = ~0x0; - /* - * The trace ID value for *ETM* tracers start at CPU_ID * 2 + 0x10 and - * anything equal to or higher than 0x70 is reserved. Since 0x00 is - * also reserved the STM trace ID needs to be higher than 0x00 and - * lowner than 0x10. - */ - drvdata->traceid = 0x1; - /* Set invariant transaction timing on all channels */ bitmap_clear(drvdata->chs.guaranteed, 0, drvdata->numsp); } @@ -854,7 +830,7 @@ static void stm_init_generic_data(struct stm_drvdata *drvdata, static int stm_probe(struct amba_device *adev, const struct amba_id *id) { - int ret; + int ret, trace_id; void __iomem *base; struct device *dev = &adev->dev; struct coresight_platform_data *pdata = NULL; @@ -938,12 +914,22 @@ static int stm_probe(struct amba_device *adev, const struct amba_id *id) goto stm_unregister; } + trace_id = coresight_trace_id_get_system_id(); + if (trace_id < 0) { + ret = trace_id; + goto cs_unregister; + } + drvdata->traceid = (u8)trace_id; + pm_runtime_put(&adev->dev); dev_info(&drvdata->csdev->dev, "%s initialized\n", (char *)coresight_get_uci_data(id)); return 0; +cs_unregister: + coresight_unregister(drvdata->csdev); + stm_unregister: stm_unregister_device(&drvdata->stm); return ret; @@ -953,6 +939,7 @@ static void stm_remove(struct amba_device *adev) { struct stm_drvdata *drvdata = dev_get_drvdata(&adev->dev); + coresight_trace_id_put_system_id(drvdata->traceid); coresight_unregister(drvdata->csdev); stm_unregister_device(&drvdata->stm);