From patchwork Tue Aug 9 22:33:53 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mike Leach X-Patchwork-Id: 12940038 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 8652FC19F2D for ; Tue, 9 Aug 2022 22:36:07 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:MIME-Version:List-Subscribe:List-Help: List-Post:List-Archive:List-Unsubscribe:List-Id:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=HT348nyF9QlW5fcU5Ntsmog/86kz9hUSWYshXHm6r4M=; b=bfqaWK6Ykqn85n sv0M5F1qulGTlejBdlF9+Gy9gPOF0t77c2OksR77zuPVvd9as6ImTYdc9ZTotDFqhA2EDnj1TRExu ohPJBG8qe1d0NSvfn5ia4NfzzM4UnYfUq5Ovy43dvAjeq371SALxtvkKjAbsaQz3/72PfHGkIofhR oykf8rR4DoOhQMN6wn5u4Vdn3wcp9cfWQIMjmhSbBhh/E6wuOVoEh5vnJsIiZ286FcmbfX2Bq4mH4 ZiAlknhUMliDFODj45MM3LDn84aF4EwWSk0lbJX//F9FYyD/wiREQEY035r6TNGLKRJz1RN9+KkOT inFXL6OUleTqf1izfKZA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1oLXoQ-0073o3-UN; Tue, 09 Aug 2022 22:34:59 +0000 Received: from mail-wm1-x32e.google.com ([2a00:1450:4864:20::32e]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1oLXng-0073XV-Md for linux-arm-kernel@lists.infradead.org; Tue, 09 Aug 2022 22:34:17 +0000 Received: by mail-wm1-x32e.google.com with SMTP id ay36-20020a05600c1e2400b003a4e30d7995so142501wmb.5 for ; Tue, 09 Aug 2022 15:34:12 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=lYcuc9rgeB5uU+5i7r38Aemp+oMPCEAMe0bEyvRkXHU=; b=fOlX3zHl2q80OBOqjiYyKhFLa4DgXfSYcCGD1jD5SGQ6VL7Lwf2UCoPUK441ibe+tR blFN8JJPuPmWHcFHj/Gs7SvCORuGrTfcnoJljmTqrmlXUPpFXD3L1EQwW0DNLaEsp8w1 vADIQeYQvLVBxkUoqUZ4O0/tJhRMxqBKFLmxZSNsMamd3YhSlFVTMomzdyDNxV7wRF2b MgMmkpeg17cn9S+WXTbh6mxT4W33nMA2thiDctH80kUEWcDa1zrhZ84n8exLggN5oANj /zuxb2Rdc3WQqiQbeA320yYuJxIZpJa8nf9DqEqy3W3jUiVyEunpOJ6Lh53io4C0VlJg NWLA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=lYcuc9rgeB5uU+5i7r38Aemp+oMPCEAMe0bEyvRkXHU=; b=1d2obbEpg1hkb6BUwkK9xJJObOl72LbfDMhTedwz9Me2zdqeWIrWv1pOuPLzAGNlzV d1FZEWVZ7DS6hTXjSkpWVN3H634fWBtyGZGXaA/CzpIZf376eh0S5823Vp5+rZYN2v7c tUCQISkq2IWpBAqPRMahn8SrAccYL7JpNXEzGL3arGl1urXYD4u2kmAJP8o/Suet0m8S gxpNqnlnCCl53XepDNFYalPwQkv//DuDxVSQnmfPE0+H3j+n4un+ZmSUvBr3oUgQjveX 3+Tgj4NddhYbskNaC3y04uUwewDAqErJO5E5U9oLDmaO9j/csoeJXAU+1b1drmwoEc9v WMmg== X-Gm-Message-State: ACgBeo1Avf3Kx5j5RgRQkHdYfYTN7lnsgx+sxwFv+pgGr9S2HEffTBRy FNuaR/bwUiTMh0fIH/Xy69rR1w== X-Google-Smtp-Source: AA6agR6F4IYAkHtVjEr2KwObCL/Q2qWfMR30WbELGiwB3CHUe/Xi0FMBwikyvYrxnFu0xk/83MT3aA== X-Received: by 2002:a7b:c003:0:b0:39c:5642:e415 with SMTP id c3-20020a7bc003000000b0039c5642e415mr299673wmb.111.1660084451168; Tue, 09 Aug 2022 15:34:11 -0700 (PDT) Received: from linaro.org ([2a00:23c5:6809:2201:a6:74a6:5a0e:f3e2]) by smtp.gmail.com with ESMTPSA id e20-20020a05600c4b9400b003a2cf1ba9e2sm311650wmp.6.2022.08.09.15.34.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 09 Aug 2022 15:34:10 -0700 (PDT) From: Mike Leach To: coresight@lists.linaro.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Cc: mathieu.poirier@linaro.org, suzuki.poulose@arm.com, peterz@infradead.org, mingo@redhat.com, acme@kernel.org, linux-perf-users@vger.kernel.org, leo.yan@linaro.org, quic_jinlmao@quicinc.com, Mike Leach Subject: [PATCH v3 05/13] coresight: etm3x: Update ETM3 driver to use Trace ID API Date: Tue, 9 Aug 2022 23:33:53 +0100 Message-Id: <20220809223401.24599-6-mike.leach@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20220809223401.24599-1-mike.leach@linaro.org> References: <20220809223401.24599-1-mike.leach@linaro.org> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220809_153412_763518_A4FE48F4 X-CRM114-Status: GOOD ( 25.20 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Use the TraceID API to allocate ETM trace IDs dynamically. As with the etm4x we allocate on enable / disable for perf, allocate on enable / reset for sysfs. Additionally we allocate on sysfs file read as both perf and sysfs can read the ID before enabling the hardware. Remove sysfs option to write trace ID - which is inconsistent with both the dynamic allocation method and the fixed allocation method previously used. Signed-off-by: Mike Leach Reported-by: kernel test robot Reported-by: kernel test robot --- drivers/hwtracing/coresight/coresight-etm.h | 2 + .../coresight/coresight-etm3x-core.c | 77 +++++++++++++++++-- .../coresight/coresight-etm3x-sysfs.c | 27 ++----- 3 files changed, 79 insertions(+), 27 deletions(-) diff --git a/drivers/hwtracing/coresight/coresight-etm.h b/drivers/hwtracing/coresight/coresight-etm.h index f3ab96eaf44e..3667428d38b6 100644 --- a/drivers/hwtracing/coresight/coresight-etm.h +++ b/drivers/hwtracing/coresight/coresight-etm.h @@ -287,4 +287,6 @@ int etm_get_trace_id(struct etm_drvdata *drvdata); void etm_set_default(struct etm_config *config); void etm_config_trace_mode(struct etm_config *config); struct etm_config *get_etm_config(struct etm_drvdata *drvdata); +int etm_read_alloc_trace_id(struct etm_drvdata *drvdata); +void etm_release_trace_id(struct etm_drvdata *drvdata); #endif diff --git a/drivers/hwtracing/coresight/coresight-etm3x-core.c b/drivers/hwtracing/coresight/coresight-etm3x-core.c index d0ab9933472b..c4e7b3337a5c 100644 --- a/drivers/hwtracing/coresight/coresight-etm3x-core.c +++ b/drivers/hwtracing/coresight/coresight-etm3x-core.c @@ -32,6 +32,7 @@ #include "coresight-etm.h" #include "coresight-etm-perf.h" +#include "coresight-trace-id.h" /* * Not really modular but using module_param is the easiest way to @@ -490,18 +491,67 @@ static int etm_trace_id(struct coresight_device *csdev) return etm_get_trace_id(drvdata); } +int etm_read_alloc_trace_id(struct etm_drvdata *drvdata) +{ + int trace_id; + + /* trace id function has its own lock */ + trace_id = coresight_trace_id_get_cpu_id(drvdata->cpu); + if (IS_VALID_ID(trace_id)) + drvdata->traceid = (u8)trace_id; + else + dev_err(&drvdata->csdev->dev, + "Failed to allocate trace ID for %s on CPU%d\n", + dev_name(&drvdata->csdev->dev), drvdata->cpu); + return trace_id; +} + +static int etm_set_current_trace_id(struct etmv4_drvdata *drvdata) +{ + int trace_id; + + /* + * Set the currently allocated trace ID - perf allocates IDs + * as part of setup_aux for all CPUs it may use. + */ + trace_id = coresight_trace_id_read_cpu_id(drvdata->cpu); + if (IS_VALID_ID(trace_id)) { + drvdata->traceid = (u8)trace_id; + return 0; + } + + dev_err(&drvdata->csdev->dev, "Failed to set trace ID for %s on CPU%d\n", + dev_name(&drvdata->csdev->dev), drvdata->cpu); + + return -EINVAL; +} + +void etm_release_trace_id(struct etm_drvdata *drvdata) +{ + coresight_trace_id_put_cpu_id(drvdata->cpu); +} + static int etm_enable_perf(struct coresight_device *csdev, struct perf_event *event) { struct etm_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent); + int ret; if (WARN_ON_ONCE(drvdata->cpu != smp_processor_id())) return -EINVAL; /* Configure the tracer based on the session's specifics */ etm_parse_event_config(drvdata, event); + + /* perf allocates cpu IDs in setup aux - set the current on device */ + ret = etm_set_current_trace_id(drvdata); + if (ret < 0) + return ret; + /* And enable it */ - return etm_enable_hw(drvdata); + ret = etm_enable_hw(drvdata); + + return ret; } static int etm_enable_sysfs(struct coresight_device *csdev) @@ -512,6 +562,11 @@ static int etm_enable_sysfs(struct coresight_device *csdev) spin_lock(&drvdata->spinlock); + /* sysfs needs to allocate and set a trace ID */ + ret = etm_read_alloc_trace_id(drvdata); + if (ret < 0) + goto unlock_enable_sysfs; + /* * Configure the ETM only if the CPU is online. If it isn't online * hw configuration will take place on the local CPU during bring up. @@ -528,6 +583,10 @@ static int etm_enable_sysfs(struct coresight_device *csdev) ret = -ENODEV; } + if (ret) + etm_release_trace_id(drvdata); + +unlock_enable_sysfs: spin_unlock(&drvdata->spinlock); if (!ret) @@ -611,6 +670,9 @@ static void etm_disable_perf(struct coresight_device *csdev) coresight_disclaim_device_unlocked(csdev); CS_LOCK(drvdata->base); + + /* The perf event will release trace ids when it is destroyed */ + } static void etm_disable_sysfs(struct coresight_device *csdev) @@ -635,6 +697,13 @@ static void etm_disable_sysfs(struct coresight_device *csdev) spin_unlock(&drvdata->spinlock); cpus_read_unlock(); + /* + * we only release trace IDs when resetting sysfs. + * This permits sysfs users to read the trace ID after the trace + * session has completed. This maintains operational behaviour with + * prior trace id allocation method + */ + dev_dbg(&csdev->dev, "ETM tracing disabled\n"); } @@ -781,11 +850,6 @@ static void etm_init_arch_data(void *info) CS_LOCK(drvdata->base); } -static void etm_init_trace_id(struct etm_drvdata *drvdata) -{ - drvdata->traceid = coresight_get_trace_id(drvdata->cpu); -} - static int __init etm_hp_setup(void) { int ret; @@ -871,7 +935,6 @@ static int etm_probe(struct amba_device *adev, const struct amba_id *id) if (etm_arch_supported(drvdata->arch) == false) return -EINVAL; - etm_init_trace_id(drvdata); etm_set_default(&drvdata->config); pdata = coresight_get_platform_data(dev); diff --git a/drivers/hwtracing/coresight/coresight-etm3x-sysfs.c b/drivers/hwtracing/coresight/coresight-etm3x-sysfs.c index 68fcbf4ce7a8..fde028e43c92 100644 --- a/drivers/hwtracing/coresight/coresight-etm3x-sysfs.c +++ b/drivers/hwtracing/coresight/coresight-etm3x-sysfs.c @@ -85,6 +85,7 @@ static ssize_t reset_store(struct device *dev, } etm_set_default(config); + etm_release_trace_id(drvdata); spin_unlock(&drvdata->spinlock); } @@ -1189,30 +1190,16 @@ static DEVICE_ATTR_RO(cpu); static ssize_t traceid_show(struct device *dev, struct device_attribute *attr, char *buf) { - unsigned long val; - struct etm_drvdata *drvdata = dev_get_drvdata(dev->parent); - - val = etm_get_trace_id(drvdata); - - return sprintf(buf, "%#lx\n", val); -} - -static ssize_t traceid_store(struct device *dev, - struct device_attribute *attr, - const char *buf, size_t size) -{ - int ret; - unsigned long val; + int trace_id; struct etm_drvdata *drvdata = dev_get_drvdata(dev->parent); - ret = kstrtoul(buf, 16, &val); - if (ret) - return ret; + trace_id = etm_read_alloc_trace_id(drvdata); + if (trace_id < 0) + return trace_id; - drvdata->traceid = val & ETM_TRACEID_MASK; - return size; + return sysfs_emit(buf, "%#x\n", trace_id); } -static DEVICE_ATTR_RW(traceid); +static DEVICE_ATTR_RO(traceid); static struct attribute *coresight_etm_attrs[] = { &dev_attr_nr_addr_cmp.attr,