From patchwork Tue Aug 9 22:33:55 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mike Leach X-Patchwork-Id: 12940041 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 6490FC19F2D for ; Tue, 9 Aug 2022 22:37:36 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:MIME-Version:List-Subscribe:List-Help: List-Post:List-Archive:List-Unsubscribe:List-Id:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=05JRnYg0Ryxvg/LbYicIdficEPWZj9pSGeJkCRjdmZ4=; b=fjSgXG6O/gAxor D0V572SIoBZYxYiL0uvj6Wh3v9RijlQBd4/1xfqC8M6M3GFSxhKBBsqiTMh39vxHgjk77F00AEYcX 63IaMl154zh2bwMRpzpkzOhhTZt1JZi+UBF+BPvBMPFPe0SdF7mEZ3Em/xwgxv7D5hgC7jTh9xlce TpdHSOcAYNWgMncyhY8mGZorQDlITX1HF2k7+Yf6ZgH04IuEymPrhJzGbxORrmvwyjnz8vmI4oGz2 5FoH46WJ+qvyEnph6nhHVTstWoykNc/FCMRu00PFwXO6QCHNVL4DIjOUsUr11d1ndZgp4ERRPu2nx wU3SZWXt+uYqroRQjvgQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1oLXpl-0074SG-LS; Tue, 09 Aug 2022 22:36:22 +0000 Received: from mail-wm1-f44.google.com ([209.85.128.44]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1oLXnk-0073Zd-24 for linux-arm-kernel@lists.infradead.org; Tue, 09 Aug 2022 22:34:20 +0000 Received: by mail-wm1-f44.google.com with SMTP id ay39-20020a05600c1e2700b003a5503a80cfso142317wmb.2 for ; Tue, 09 Aug 2022 15:34:14 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=8Wmt5utEn01FakaCjSV6ZsTv6W9xbPzrClska04k2gs=; b=WBnf+tQjhMAZgTQMlUHcR2hov53bx5/uA6zrlkjEJmGNKSbhwfGSWJ51ZsiLPQ447o pIeeoODnoSHLz55YY2PwDtBU8h0/4+fOUDrcbNjEXsA5/WCTcixFAE0XTZ9UvZwcOVmh MqemA//x4Oq7sWKVSmkU/jJDeSTLOS9qKMEETQFZojLpQf73m1j1FbAnAjLcocqmvCFU IpXKJrLwXLYbQSwUfmszaCVhbnGJpQtKg8ifqJ6yDwsU+VuJHhrxnmqn3tG6EI2hQwQo LfPSHf7HXnFqIAEZYhZ8/HYDVTfSmD0PDI5LUWHPjgE8DnkfIF2ttWiRFXy+H4VOpiat 4qig== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=8Wmt5utEn01FakaCjSV6ZsTv6W9xbPzrClska04k2gs=; b=kzr/5OlPQ9rmVkKOY1ra8otrpgNJT+VkPGGWeLnYJEV3Itqd3tpoE0a7ns24vWNs8f v0eq38w40SYcKhL2fQ9RogVYf9AyO2cQuGN8wFtGa2/FtNc521k8LPfkxMnLqGmAV/Vo hxUEpfDecG+gNqtvyP5hAyMrxfxOIpjjsCb5nq9wJGU97Ty8WxSLpP1IqzYa/94FMmUU ZDuXRg96rC1KlznnQ0c4Ry9NNgxzMfdk2QA3klO370MEJHNbgLxbbjvcUA0F5K3TcM8o EA1rO01llloJhB71awjlhyUL25lw4a5QOQPJv/6QQHrz4gRSXIQvt3n9/K2eSbqSWqVS Y5hw== X-Gm-Message-State: ACgBeo25qegL5pRYJ/NIPmqdP6GD54qy9KdNJGMJ5kzjL8Xqg1uJw2nF voNb8d9dUDeC1TRsyz2ghjvyhg== X-Google-Smtp-Source: AA6agR4pcP6KnBrfBu99TLZiqpgxLRCfsBSUER8fZ3LjaD5gBMcq/O0jYwDO7xU7JMpyTinfX6DDTQ== X-Received: by 2002:a1c:2585:0:b0:3a5:2163:f33b with SMTP id l127-20020a1c2585000000b003a52163f33bmr307030wml.189.1660084453189; Tue, 09 Aug 2022 15:34:13 -0700 (PDT) Received: from linaro.org ([2a00:23c5:6809:2201:a6:74a6:5a0e:f3e2]) by smtp.gmail.com with ESMTPSA id e20-20020a05600c4b9400b003a2cf1ba9e2sm311650wmp.6.2022.08.09.15.34.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 09 Aug 2022 15:34:12 -0700 (PDT) From: Mike Leach To: coresight@lists.linaro.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Cc: mathieu.poirier@linaro.org, suzuki.poulose@arm.com, peterz@infradead.org, mingo@redhat.com, acme@kernel.org, linux-perf-users@vger.kernel.org, leo.yan@linaro.org, quic_jinlmao@quicinc.com, Mike Leach Subject: [PATCH v3 07/13] coresight: perf: traceid: Add perf notifiers for Trace ID Date: Tue, 9 Aug 2022 23:33:55 +0100 Message-Id: <20220809223401.24599-8-mike.leach@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20220809223401.24599-1-mike.leach@linaro.org> References: <20220809223401.24599-1-mike.leach@linaro.org> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220809_153416_153458_3240BB4B X-CRM114-Status: GOOD ( 16.68 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Adds in notifier calls to the trace ID allocator that perf events are starting and stopping. This ensures that Trace IDs associated with CPUs remain the same throughout the perf session, and are only released when all perf sessions are complete. Signed-off-by: Mike Leach --- drivers/hwtracing/coresight/coresight-etm-perf.c | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/drivers/hwtracing/coresight/coresight-etm-perf.c b/drivers/hwtracing/coresight/coresight-etm-perf.c index 43bbd5dc3d3b..6166f716a6ac 100644 --- a/drivers/hwtracing/coresight/coresight-etm-perf.c +++ b/drivers/hwtracing/coresight/coresight-etm-perf.c @@ -22,6 +22,7 @@ #include "coresight-etm-perf.h" #include "coresight-priv.h" #include "coresight-syscfg.h" +#include "coresight-trace-id.h" static struct pmu etm_pmu; static bool etm_perf_up; @@ -228,8 +229,12 @@ static void free_event_data(struct work_struct *work) if (!(IS_ERR_OR_NULL(*ppath))) coresight_release_path(*ppath); *ppath = NULL; + coresight_trace_id_put_cpu_id(cpu); } + /* mark perf event as done for trace id allocator */ + coresight_trace_id_perf_stop(); + free_percpu(event_data->path); kfree(event_data); } @@ -300,6 +305,7 @@ static void *etm_setup_aux(struct perf_event *event, void **pages, { u32 id, cfg_hash; int cpu = event->cpu; + int trace_id; cpumask_t *mask; struct coresight_device *sink = NULL; struct coresight_device *user_sink = NULL, *last_sink = NULL; @@ -316,6 +322,9 @@ static void *etm_setup_aux(struct perf_event *event, void **pages, sink = user_sink = coresight_get_sink_by_id(id); } + /* tell the trace ID allocator that a perf event is starting up */ + coresight_trace_id_perf_start(); + /* check if user wants a coresight configuration selected */ cfg_hash = (u32)((event->attr.config2 & GENMASK_ULL(63, 32)) >> 32); if (cfg_hash) { @@ -388,6 +397,13 @@ static void *etm_setup_aux(struct perf_event *event, void **pages, continue; } + /* ensure we can allocate a trace ID for this CPU */ + trace_id = coresight_trace_id_get_cpu_id(cpu); + if (!IS_VALID_ID(trace_id)) { + cpumask_clear_cpu(cpu, mask); + continue; + } + *etm_event_cpu_path_ptr(event_data, cpu) = path; }