From patchwork Fri Aug 12 06:16:48 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Matt Ranostay X-Patchwork-Id: 12941932 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 7D925C00140 for ; Fri, 12 Aug 2022 06:18:36 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:Message-ID:Date:Subject:CC :To:From:Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:In-Reply-To:References: List-Owner; bh=qi/tMI8WCLKQ+24CuXwZyQRfXNLedUks9ictgq0ftIU=; b=qtLSGsPk5mUwJE T4rveVGQslVmnmWKO6Ydf7O9uvCPhUzPHL5Y9QoZawaXApvT+oIiGupOrbaWjSDi7d8aItQqA4hL7 cY9MpPbtuhrPcxDSD1V4TFNJsmlOryFyjRv4YYc3NBDXS4n3DPcXUZ8yevVzqUtLQXBJIw4CqPMO+ tqhvYyzIko5gcatYR64Bkq8yp10Kyi8sFKpmtuF1VDWO8DZe1KF7djQMNX7N6aeAlSrGQBWPbSd1o XxYadXR3DUTJxWHC6zpzBrl6rHmaJqvJ2a1KE+gS6st816acFkN9tKPUf8xcR7Kua7DrQhjZdBl+w nbQEd9XMH6XG3j4UsCYA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1oMNyo-00GPJK-UQ; Fri, 12 Aug 2022 06:17:11 +0000 Received: from lelv0142.ext.ti.com ([198.47.23.249]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1oMNyl-00GOzg-7k for linux-arm-kernel@lists.infradead.org; Fri, 12 Aug 2022 06:17:08 +0000 Received: from lelv0266.itg.ti.com ([10.180.67.225]) by lelv0142.ext.ti.com (8.15.2/8.15.2) with ESMTP id 27C6GvIS088066 for ; Fri, 12 Aug 2022 01:16:57 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1660285017; bh=lfOhOT83uV/GB83kpqA5w0vcSJMcnhWQd2CfiaA7ds0=; h=From:To:CC:Subject:Date; b=zBHTXGqPEkr402/nv+u7wJUw66oVG6IEAIsko45JkoWHF9e8iwYtQlKP2FVyJPSq6 LolWRfl4RfeqH9sbi2sOQ5xXaPvyeT/6ADqJurF3syiMIkr7RSwgpDXihBJE1sljKZ so3LZ/TAI65mJSWmYq/EqOsbJ9xQ3T/Xowr+xb2E= Received: from DLEE103.ent.ti.com (dlee103.ent.ti.com [157.170.170.33]) by lelv0266.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 27C6GvxW074513 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL) for ; Fri, 12 Aug 2022 01:16:57 -0500 Received: from DLEE111.ent.ti.com (157.170.170.22) by DLEE103.ent.ti.com (157.170.170.33) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.6; Fri, 12 Aug 2022 01:16:56 -0500 Received: from fllv0039.itg.ti.com (10.64.41.19) by DLEE111.ent.ti.com (157.170.170.22) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.6 via Frontend Transport; Fri, 12 Aug 2022 01:16:56 -0500 Received: from ubuntu.ent.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by fllv0039.itg.ti.com (8.15.2/8.15.2) with ESMTP id 27C6Gp5W080983; Fri, 12 Aug 2022 01:16:53 -0500 From: Matt Ranostay To: CC: Matt Ranostay Subject: [PATCH] arm64: dts: ti: k3-j7200: fix main pinmux range Date: Thu, 11 Aug 2022 23:16:48 -0700 Message-ID: <20220812061648.4926-1-mranostay@ti.com> X-Mailer: git-send-email 2.36.1 MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220811_231707_430578_E468E691 X-CRM114-Status: GOOD ( 12.55 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Range size of 0x2b4 was incorrect since there isn't 173 configurable pins for muxing. Additionally there is a non-addessable region in the mapping which requires spliting into two ranges. main_pmx0 -> 71 pins main_pmx1 -> 2 pins Fixes: d361ed88455f ("arm64: dts: ti: Add support for J7200 SoC") Signed-off-by: Matt Ranostay --- Forgot to add linux-arm-kernel to the initial patchset CC Link: https://lore.kernel.org/linux-kernel/20220805174339.823634-1-mranostay@ti.com/ arch/arm64/boot/dts/ti/k3-j7200-main.dtsi | 11 ++++++++++- 1 file changed, 10 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi b/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi index 16684a2f054d..a713de57056f 100644 --- a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi @@ -295,7 +295,16 @@ cpts@310d0000 { main_pmx0: pinctrl@11c000 { compatible = "pinctrl-single"; /* Proxy 0 addressing */ - reg = <0x00 0x11c000 0x00 0x2b4>; + reg = <0x00 0x11c000 0x00 0x10c>; + #pinctrl-cells = <1>; + pinctrl-single,register-width = <32>; + pinctrl-single,function-mask = <0xffffffff>; + }; + + main_pmx1: pinctrl@11c164 { + compatible = "pinctrl-single"; + /* Proxy 0 addressing */ + reg = <0x00 0x11c164 0x00 0x8>; #pinctrl-cells = <1>; pinctrl-single,register-width = <32>; pinctrl-single,function-mask = <0xffffffff>;