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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: pxi1yxYHRuJwR6NSy6Nq+UXjY6daQYDSuCistELxJ/7YyA/+75t/WgRnEyKEFiDuJzZbTeS8I0haMGlEPzZHKAjoUGEKvf6pheZs5ojC7Bsn8aIIbWQK5HoTXgjewxbx7LAW6hQzXY2QCwXpMpBaKUk0M6cNxDv5OjNCcbYh9cmG2m2kkv1ibbiYbedom88KQFIK3Y67X36cIAjrent75hfjK8P9I1a8lrYw6TZHf3Yk8B3BvlbV+A5oP6e/UEJ965hug2AVz6oV3uAIev9SHcTCWGKldGMCtJ/BRcs87n6r+T3h141pi41FlkS2neiOAD3ngBn8WRYaBOzYz4AEbK4AmaLXI04/WPfsYTZJN5F8zgrrWYUI70ZzlArODGbwP7WhUJA3D6ULzHz8pDadNhmqJl8jZ4RKZEqgx3Kdw1o7pJwLxCr1UHDv9eX3It7/X+o58uIs/wbhZP+uosrKn73fsjiSxj3Z1PMS9yjJOlsju3hTpPAPB3NesOGyJ4u37pqtUYKfnTOAKqBb/4ddnYyHLgkZ57eHRN/tUF5ZHPh8v/JrVJAc7HBxof17MUCvtyuatuSaqc1O4a8Aqcd7wuyNT3sDvSl4o6tMAhIDB+0UP/5GZ/HLqI1ug92F7zv9HioBAzqB2XQn0D+YpYs/pW39c7AFLSR73MO78M7+ZDQGbgfH4HagidGb3aqJMnBwZR78TIpi0Xf+NRzytNGwo4b17dicYz7cjdFf4sio7u8GMU0K3S+ewqidRnQYZyGby59wcIYcoHXlO/sAjvqtOT24wHijfsfPSYD5DusR8JCdZIc+Q/d75wkaAnoPxCt0ncO+ioc12eL78s41MZL7r8AiB3MVIEHKQZzjwQWypM0EjtAy2p+AZpdDskuHo9T/olrNUvFroSf5eu9qOvigvzfrOKS0/u5T7drx+iwRGOuX9m9nLxC3x3D2LA2TVoNxp+Yxy/i5VDVXrqippHFoSYxh8XzAYWggmohx1W5l+B/Geohd5G+fNImhEi87TezEPQR0C6CGRf2s/NcrzhuuND3n7bfAJz7Z7ZiTwL+ozCX1SgkxUSPA8fljkQ9KwRhecP9oH/oZeWM4yuqKu/vl3jhdYyGoj6b0lHQdVRN6q+HdTrvXv5A8YoEnrFDgZBP8C662S8PB+LIodPO7wC9gd/PaJo6BjxWIqZd6q2ION5w3qYTQutUktj+kSkRDhSUZzZnbP+FBMdlQD3ZNPUuWZZGJIJlDfUJkV9eiXht1ehsRT4i8qScKxNX/AYtYFb2+Cy0wFANZjJ08/z4LB/Z4U9o7owd3RF9MBra6EAUBoYv8mZOqhryBFZIFhZXmpKd2tRLrbfXFGA0Tz124qFQbDKBVkZulfcjFd4e2AesxJNloddGbvvSafLsNb+E+bcv7Vl4dVq66UaAV/pTMSc89caeXYReY4ZjU/Kq9299QTNJGTHNfSJqsNk95NB0PmdsN4BdlKvlfahSaVNncoxCPsYy4unlBxzjIPRPfqzI343OeC6NhufalkhFK5R2mNtOhssqX+8BLCRdQycN59CtUh/WSvakkuED9ydLBqDFgTsKWD+pN5kfsY+w6qFUv685e X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: f7b74b96-7dd1-4f00-3c74-08da7f06bba7 X-MS-Exchange-CrossTenant-AuthSource: PAXPR04MB9186.eurprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 15 Aug 2022 21:40:12.2739 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: NjQxUPU7tI4J+UvR4+4OLgGEjzAZs+4ZFM5XYJwD9xbvoYpQJcjY4j36FW5HqCxCvcQ1XniuXkL/yDlIhT8RxA== X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM5PR0401MB2580 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220815_144018_853354_308C0A5C X-CRM114-Status: GOOD ( 14.07 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org I.MX mu support generate irq by write a register. Provide msi controller support so other driver such as PCI EP can use it by standard msi interface as doorbell. Signed-off-by: Frank Li --- .../interrupt-controller/fsl,mu-msi.yaml | 98 +++++++++++++++++++ 1 file changed, 98 insertions(+) create mode 100644 Documentation/devicetree/bindings/interrupt-controller/fsl,mu-msi.yaml diff --git a/Documentation/devicetree/bindings/interrupt-controller/fsl,mu-msi.yaml b/Documentation/devicetree/bindings/interrupt-controller/fsl,mu-msi.yaml new file mode 100644 index 0000000000000..ac07b138e24c0 --- /dev/null +++ b/Documentation/devicetree/bindings/interrupt-controller/fsl,mu-msi.yaml @@ -0,0 +1,98 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/interrupt-controller/fsl,mu-msi.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Freescale/NXP i.MX Messaging Unit (MU) work as msi controller + +maintainers: + - Frank Li + +description: | + The Messaging Unit module enables two processors within the SoC to + communicate and coordinate by passing messages (e.g. data, status + and control) through the MU interface. The MU also provides the ability + for one processor (A side) to signal the other processor (B side) using + interrupts. + + Because the MU manages the messaging between processors, the MU uses + different clocks (from each side of the different peripheral buses). + Therefore, the MU must synchronize the accesses from one side to the + other. The MU accomplishes synchronization using two sets of matching + registers (Processor A-facing, Processor B-facing). + + MU can work as msi interrupt controller to do doorbell + +allOf: + - $ref: /schemas/interrupt-controller/msi-controller.yaml# + +properties: + compatible: + enum: + - fsl,imx6sx-mu-msi + - fsl,imx7ulp-mu-msi + - fsl,imx8ulp-mu-msi + - fsl,imx8ulp-mu-msi-s4 + + reg: + items: + - description: a side register base address + - description: b side register base address + + reg-names: + items: + - const: processor a-facing + - const: processor b-facing + + interrupts: + description: a side interrupt number. + maxItems: 1 + + clocks: + maxItems: 1 + + power-domains: + items: + - description: a side power domain + - description: b side power domain + + power-domain-names: + items: + - const: processor a-facing + - const: processor b-facing + + interrupt-controller: true + + msi-controller: true + + "#msi-cells": + const: 0 + +required: + - compatible + - reg + - interrupts + - interrupt-controller + - msi-controller + +additionalProperties: false + +examples: + - | + #include + #include + + msi-controller@5d270000 { + compatible = "fsl,imx6sx-mu-msi"; + msi-controller; + #msi-cells = <0>; + interrupt-controller; + reg = <0x5d270000 0x10000>, /* A side */ + <0x5d300000 0x10000>; /* B side */ + reg-names = "processor a-facing", "processor b-facing"; + interrupts = ; + power-domains = <&pd IMX_SC_R_MU_12A>, + <&pd IMX_SC_R_MU_12B>; + power-domain-names = "processor a-facing", "processor b-facing"; + };