From patchwork Wed Aug 17 08:07:53 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Balsam CHIHI X-Patchwork-Id: 12945635 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 8592AC25B08 for ; Wed, 17 Aug 2022 08:12:07 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=UI6B4n6rTH4ITAhJ8YZcNyjWWjDjHV9mNTSXw6p/FWM=; b=xvSWI9gYbNhUDH vMyWx+SI+BGDIJXTJgdSdG2vlPOVrPiFOofLMtKWPhWTwaQpEesRG3vx3drliy+7Np1l4vD0AHslJ yDMzP8RlrvWYx7GeP9WBBL/5mTHBYoLDXQVHj0R3SBAmTYNWa2K137xQ1WRb7Okg2/qWWVD7WYeUS tEuRCa4FS3hRVvB/HPxnCSKY62yxVEzeiiAcdbJZqmwNLlK+iJdj/ZlPv46e3fKS5vK1/Nh40Mcui +N1rzdQxljYORrzg6z+OP5t0CoXHIT6qHAELQJhRA5ZeeMuqdaFTMDm/VnxMU4JgaTthkHUvPZwTl t+DLte+7++sPrmugEnfw==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1oOE8P-00EcRk-NG; Wed, 17 Aug 2022 08:10:42 +0000 Received: from mail-wr1-x42b.google.com ([2a00:1450:4864:20::42b]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1oOE6V-00EZHM-3r for linux-arm-kernel@lists.infradead.org; Wed, 17 Aug 2022 08:08:45 +0000 Received: by mail-wr1-x42b.google.com with SMTP id n7so4095035wrv.4 for ; Wed, 17 Aug 2022 01:08:40 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20210112.gappssmtp.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc; bh=LWK95oP5oKx5jLZsARdUZBbefoGwp+gOvhma7vrlCpI=; b=f0o8HbL81Cbajn0LlWxCI23dsDL/AOMSWSwK9bLg3BtFqxuu0TQnlZgMI7NIfD1j/x VONDXYw5T42+UTm7ljFx6jHpNiDCK6bfieHRhCGZ6WLnonO8sStKp2ASsUwYgTMEbiNl Afs4hhndKZkov9gggCnJYANns2YJByAxPRFXqkaQAfmPPCIyJ75jKKAqkRf6seXuFgjW Fp9w8Ia4eHjbHEAmhlmX9U/S2WHlRxof7+BEYGG4KB9UmHBZLCXv9vIRysONaywC7MlD UcNpYySrxUFzJQkidtCvuy3ozSDwb8ItzxUKCL4YwZuXP4v3fVyig5DM+bB2M2y694sQ XAcw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc; bh=LWK95oP5oKx5jLZsARdUZBbefoGwp+gOvhma7vrlCpI=; b=zMf2y4oijkHHDicOZLC6+YVjXxAvIlci48NiC8/Qx/Rm2AYwqRBG7oHsHNPhOyeYHe AX2G3yVtcV1q72uZ9BWlSajxvouKDTPuSA50GgHKLD2AnxpD9OI8n0+/lVyMkvIu5ip6 fxlqLZs58ToZ3cF6TsMCCxe2ljQoSbWV/gEtmOFXYFBzOUKIBftvcRo65QbWEqL6k2ey EeheNsRBE3mYWx+2Xrmi1jXcTGLr90q8A49XnFAfoeWQwgxSK7b7Q0frRfLcS3r8ju3b ahfP3MiQmTmkiH5O2PW1JMWkoPwlQw/6OHyVj4sM+9yADAXPzXK3Z9OetltvsvIqOhz3 vIHw== X-Gm-Message-State: ACgBeo1jADFAhdqGMuFdcPZJdZSW4S3lw6gSdC4IN6iqe5KQYGqWsTpq TKw9dFozKt7a/lVrqZvcFezMXA== X-Google-Smtp-Source: AA6agR4nxG9zqxTof6Y+siXBdw1kqtlHb/D0yV1+6gVF3PSI/A35+NZWfSjXcxpiP1+cNMMLqFn9kQ== X-Received: by 2002:adf:de91:0:b0:225:2609:27c5 with SMTP id w17-20020adfde91000000b00225260927c5mr808023wrl.252.1660723719447; Wed, 17 Aug 2022 01:08:39 -0700 (PDT) Received: from Balsam-ThinkPad-T480.civfrance.com (58.188.158.77.rev.sfr.net. [77.158.188.58]) by smtp.gmail.com with ESMTPSA id u15-20020a05600c19cf00b003a54d610e5fsm1391992wmq.26.2022.08.17.01.08.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 17 Aug 2022 01:08:39 -0700 (PDT) From: bchihi@baylibre.com To: rafael@kernel.org, rui.zhang@intel.com, daniel.lezcano@linaro.org, amitk@kernel.org Cc: linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, khilman@baylibre.com, mka@chromium.org, robh+dt@kernel.org, krzk+dt@kernel.org, matthias.bgg@gmail.com, p.zabel@pengutronix.de, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, james.lo@mediatek.com, fan.chen@mediatek.com, louis.yu@mediatek.com, rex-bc.chen@mediatek.com, abailon@baylibre.com Subject: [PATCH v9,3/7] arm64: dts: mt8192: Add thermal zones and thermal nodes Date: Wed, 17 Aug 2022 10:07:53 +0200 Message-Id: <20220817080757.352021-4-bchihi@baylibre.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220817080757.352021-1-bchihi@baylibre.com> References: <20220817080757.352021-1-bchihi@baylibre.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220817_010843_267161_523C7F0D X-CRM114-Status: GOOD ( 10.43 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org From: Balsam CHIHI Add thermal zones and thermal nodes for the mt8192. Signed-off-by: Balsam CHIHI --- arch/arm64/boot/dts/mediatek/mt8192.dtsi | 111 +++++++++++++++++++++++ 1 file changed, 111 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi index cbae5a5ee4a0..59ef4da06a70 100644 --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi @@ -12,6 +12,7 @@ #include #include #include +#include / { compatible = "mediatek,mt8192"; @@ -599,6 +600,28 @@ spi0: spi@1100a000 { status = "disabled"; }; + lvts_ap: thermal-sensor@1100b000 { + compatible = "mediatek,mt8192-lvts-ap"; + #thermal-sensor-cells = <1>; + reg = <0 0x1100b000 0 0x1000>; + interrupts = ; + clocks = <&infracfg CLK_INFRA_THERM>; + resets = <&infracfg MT8192_INFRA_RST0_THERM_CTRL_SWRST>; + nvmem-cells = <&lvts_e_data1>; + nvmem-cell-names = "lvts_calib_data1"; + }; + + lvts_mcu: thermal-sensor@11278000 { + compatible = "mediatek,mt8192-lvts-mcu"; + #thermal-sensor-cells = <1>; + reg = <0 0x11278000 0 0x1000>; + interrupts = ; + clocks = <&infracfg CLK_INFRA_THERM>; + resets = <&infracfg MT8192_INFRA_RST4_THERM_CTRL_MCU_SWRST>; + nvmem-cells = <&lvts_e_data1>; + nvmem-cell-names = "lvts_calib_data1"; + }; + spi1: spi@11010000 { compatible = "mediatek,mt8192-spi", "mediatek,mt6765-spi"; @@ -1457,4 +1480,92 @@ larb2: larb@1f002000 { power-domains = <&spm MT8192_POWER_DOMAIN_MDP>; }; }; + + thermal_zones: thermal-zones { + cpu0-thermal { + polling-delay = <0>; + polling-delay-passive = <0>; + thermal-sensors = <&lvts_mcu 0>; + }; + cpu1-thermal { + polling-delay = <0>; + polling-delay-passive = <0>; + thermal-sensors = <&lvts_mcu 1>; + }; + cpu2-thermal { + polling-delay = <0>; + polling-delay-passive = <0>; + thermal-sensors = <&lvts_mcu 2>; + }; + cpu3-thermal { + polling-delay = <0>; + polling-delay-passive = <0>; + thermal-sensors = <&lvts_mcu 3>; + }; + cpu4-thermal { + polling-delay = <0>; + polling-delay-passive = <0>; + thermal-sensors = <&lvts_mcu 4>; + }; + cpu5-thermal { + polling-delay = <0>; + polling-delay-passive = <0>; + thermal-sensors = <&lvts_mcu 5>; + }; + cpu6-thermal { + polling-delay = <0>; + polling-delay-passive = <0>; + thermal-sensors = <&lvts_mcu 6>; + }; + cpu7-thermal { + polling-delay = <0>; + polling-delay-passive = <0>; + thermal-sensors = <&lvts_mcu 7>; + }; + vpu1-thermal { + polling-delay = <0>; + polling-delay-passive = <0>; + thermal-sensors = <&lvts_ap 0>; + }; + vpu2-thermal { + polling-delay = <0>; + polling-delay-passive = <0>; + thermal-sensors = <&lvts_ap 1>; + }; + gpu1-thermal { + polling-delay = <0>; + polling-delay-passive = <0>; + thermal-sensors = <&lvts_ap 2>; + }; + gpu2-thermal { + polling-delay = <0>; + polling-delay-passive = <0>; + thermal-sensors = <&lvts_ap 3>; + }; + infra-thermal { + polling-delay = <0>; + polling-delay-passive = <0>; + thermal-sensors = <&lvts_ap 4>; + }; + cam-thermal { + polling-delay = <0>; + polling-delay-passive = <0>; + thermal-sensors = <&lvts_ap 5>; + }; + md1-thermal { + polling-delay = <0>; + polling-delay-passive = <0>; + thermal-sensors = <&lvts_ap 6>; + }; + md2-thermal { + polling-delay = <0>; + polling-delay-passive = <0>; + thermal-sensors = <&lvts_ap 7>; + }; + md3-thermal { + polling-delay = <0>; + polling-delay-passive = <0>; + thermal-sensors = <&lvts_ap 8>; + }; + }; };