| Message ID | 20220817204357.21753-5-leoyang.li@nxp.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | ls208xa dts updates | expand |
On Wed, Aug 17, 2022 at 03:43:55PM -0500, Li Yang wrote: > From: Priyanka Jain <priyanka.jain@nxp.com> > > This patch adds support for NXP LS2081ARDB board which has LS2081A SoC. > > LS2081A SoC is 40-pin derivative of LS2088A SoC. From functional > perspective both are same. Hence, LS2088a SoC dtsi file is included > from LS2081ARDB dts. > > Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> > Signed-off-by: Santan Kumar <santan.kumar@nxp.com> > Signed-off-by: Tao Yang <b31903@freescale.com> > Signed-off-by: Yogesh Gaur <yogeshnarayan.gaur@nxp.com> > Signed-off-by: Abhimanyu Saini <abhimanyu.saini@nxp.com> > Signed-off-by: Li Yang <leoyang.li@nxp.com> > --- > arch/arm64/boot/dts/freescale/Makefile | 1 + > .../boot/dts/freescale/fsl-ls2081a-rdb.dts | 131 ++++++++++++++++++ > 2 files changed, 132 insertions(+) > create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls2081a-rdb.dts > > diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile > index 2cf55534c162..bf7c448fa817 100644 > --- a/arch/arm64/boot/dts/freescale/Makefile > +++ b/arch/arm64/boot/dts/freescale/Makefile > @@ -36,6 +36,7 @@ dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1088a-rdb.dtb > dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1088a-ten64.dtb > dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2080a-qds.dtb > dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2080a-rdb.dtb > +dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2081a-rdb.dtb > dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2080a-simu.dtb > dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2088a-qds.dtb > dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2088a-rdb.dtb > diff --git a/arch/arm64/boot/dts/freescale/fsl-ls2081a-rdb.dts b/arch/arm64/boot/dts/freescale/fsl-ls2081a-rdb.dts > new file mode 100644 > index 000000000000..0148f8c93442 > --- /dev/null > +++ b/arch/arm64/boot/dts/freescale/fsl-ls2081a-rdb.dts > @@ -0,0 +1,131 @@ > +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) > +/* > + * Device Tree file for NXP LS2081A RDB Board. > + * > + * Copyright 2017 NXP > + * > + * Priyanka Jain <priyanka.jain@nxp.com> > + * > + */ > + > +/dts-v1/; > + > +#include "fsl-ls2088a.dtsi" > + > +/ { > + model = "NXP Layerscape 2081A RDB Board"; > + compatible = "fsl,ls2081a-rdb", "fsl,ls2081a"; > + > + aliases { > + serial0 = &serial0; > + serial1 = &serial1; > + }; > + > + chosen { > + stdout-path = "serial1:115200n8"; > + }; > +}; > + > +&dspi { > + status = "okay"; > + > + n25q512a: flash@0 { > + compatible = "jedec,spi-nor"; > + #address-cells = <1>; > + #size-cells = <1>; > + spi-max-frequency = <3000000>; > + reg = <0>; > + }; > +}; > + > +&esdhc { > + status = "okay"; > +}; > + > +&ifc { > + status = "disabled"; > +}; > + > +&i2c0 { > + status = "okay"; > + > + pca9547: mux@75 { > + compatible = "nxp,pca9547"; > + reg = <0x75>; > + #address-cells = <1>; > + #size-cells = <0>; > + > + i2c@1 { > + #address-cells = <1>; > + #size-cells = <0>; > + reg = <0x1>; Have a newline between properties and child node. Shawn > + rtc@51 { > + compatible = "nxp,pcf2129"; > + reg = <0x51>; > + }; > + }; > + > + i2c@2 { > + #address-cells = <1>; > + #size-cells = <0>; > + reg = <0x2>; > + > + ina220@40 { > + compatible = "ti,ina220"; > + reg = <0x40>; > + shunt-resistor = <500>; > + }; > + }; > + > + i2c@3 { > + #address-cells = <1>; > + #size-cells = <0>; > + reg = <0x3>; > + > + adt7481@4c { > + compatible = "adi,adt7461"; > + reg = <0x4c>; > + }; > + }; > + }; > +}; > + > +&qspi { > + status = "okay"; > + > + s25fs512s0: flash@0 { > + compatible = "jedec,spi-nor"; > + #address-cells = <1>; > + #size-cells = <1>; > + spi-rx-bus-width = <4>; > + spi-tx-bus-width = <4>; > + spi-max-frequency = <20000000>; > + reg = <0>; > + }; > + > + s25fs512s1: flash@1 { > + compatible = "jedec,spi-nor"; > + #address-cells = <1>; > + #size-cells = <1>; > + spi-rx-bus-width = <4>; > + spi-tx-bus-width = <4>; > + spi-max-frequency = <20000000>; > + reg = <1>; > + }; > +}; > + > +&sata0 { > + status = "okay"; > +}; > + > +&sata1 { > + status = "okay"; > +}; > + > +&usb0 { > + status = "okay"; > +}; > + > +&usb1 { > + status = "okay"; > +}; > -- > 2.37.1 >
diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile index 2cf55534c162..bf7c448fa817 100644 --- a/arch/arm64/boot/dts/freescale/Makefile +++ b/arch/arm64/boot/dts/freescale/Makefile @@ -36,6 +36,7 @@ dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1088a-rdb.dtb dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1088a-ten64.dtb dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2080a-qds.dtb dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2080a-rdb.dtb +dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2081a-rdb.dtb dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2080a-simu.dtb dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2088a-qds.dtb dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2088a-rdb.dtb diff --git a/arch/arm64/boot/dts/freescale/fsl-ls2081a-rdb.dts b/arch/arm64/boot/dts/freescale/fsl-ls2081a-rdb.dts new file mode 100644 index 000000000000..0148f8c93442 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-ls2081a-rdb.dts @@ -0,0 +1,131 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Device Tree file for NXP LS2081A RDB Board. + * + * Copyright 2017 NXP + * + * Priyanka Jain <priyanka.jain@nxp.com> + * + */ + +/dts-v1/; + +#include "fsl-ls2088a.dtsi" + +/ { + model = "NXP Layerscape 2081A RDB Board"; + compatible = "fsl,ls2081a-rdb", "fsl,ls2081a"; + + aliases { + serial0 = &serial0; + serial1 = &serial1; + }; + + chosen { + stdout-path = "serial1:115200n8"; + }; +}; + +&dspi { + status = "okay"; + + n25q512a: flash@0 { + compatible = "jedec,spi-nor"; + #address-cells = <1>; + #size-cells = <1>; + spi-max-frequency = <3000000>; + reg = <0>; + }; +}; + +&esdhc { + status = "okay"; +}; + +&ifc { + status = "disabled"; +}; + +&i2c0 { + status = "okay"; + + pca9547: mux@75 { + compatible = "nxp,pca9547"; + reg = <0x75>; + #address-cells = <1>; + #size-cells = <0>; + + i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x1>; + rtc@51 { + compatible = "nxp,pcf2129"; + reg = <0x51>; + }; + }; + + i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x2>; + + ina220@40 { + compatible = "ti,ina220"; + reg = <0x40>; + shunt-resistor = <500>; + }; + }; + + i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x3>; + + adt7481@4c { + compatible = "adi,adt7461"; + reg = <0x4c>; + }; + }; + }; +}; + +&qspi { + status = "okay"; + + s25fs512s0: flash@0 { + compatible = "jedec,spi-nor"; + #address-cells = <1>; + #size-cells = <1>; + spi-rx-bus-width = <4>; + spi-tx-bus-width = <4>; + spi-max-frequency = <20000000>; + reg = <0>; + }; + + s25fs512s1: flash@1 { + compatible = "jedec,spi-nor"; + #address-cells = <1>; + #size-cells = <1>; + spi-rx-bus-width = <4>; + spi-tx-bus-width = <4>; + spi-max-frequency = <20000000>; + reg = <1>; + }; +}; + +&sata0 { + status = "okay"; +}; + +&sata1 { + status = "okay"; +}; + +&usb0 { + status = "okay"; +}; + +&usb1 { + status = "okay"; +};