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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: YquB3eBW35wzSQsKdd9zGVXHI320eou4eaEzrGfS+f3NT51X3nGSFHIJ0tYzvT2eSIgrWPvaQpQN17755+2rZdw6E4uOViT9g/pFfr0EKHZ4B8yfMRfo8bbQPwXyi/a2PlO9uLrP3cNbCHTqTUfAi4lM8MJbDrs6zcs5nWXaq3DqedpjmEc+jtFHEMIDsKaoylaner/7ihlRw0iktx18bTSUKCytZ3+Y3AQKsM0UWWPFADvQGTr9zsAd2B5WEc5Ra6geWj5c7UtCSUkVhcE28TaB4pxOKqvluuvrr82V2mepyiN+tUtihcKBIDiqEmbA7/KeLJjvS12VnIhQqAktkinS6t0eHAF5Ze0C/tcQ6OJBpxyRAphl4Uo/YdUMN1lbdvxBW9EkDBREcFyvlu68+zc54rg6M4D4o7UPkdELo8KKRDsp/Ald0Q1gWXk67m1mrMGO7+fM3wAxQ071ZVBmNtsDteMk7FAXwaMWS46Ydph6ZZ/vdXEAUzeaPgpSXovfM8YT8ihI9f6nygfI73MCM3JpSCnKaFOkJj8jAK7tKLnho/qn7mmNc/xQu2YyXnDFgV33OXDea8Yi8wmOEBzKo3hAwfh830pYlxfYm9qXLRsaqLOFiXAGE6ijlp4O7Aof3Gk6LGoOlwoo1rmUTM4z8b9A5FEzYYcU2qjvCmPa67illQlvZtsFu/zHOnqbITVQLA8MNGovq5AcAfP1W++9FcgmhVFtpIV3wJ0PKnJfamrnZuQGOwjY/warG6zEsCa5tN2DgFJ3hYsTMyUl2GXEDVS46LWqs2iLAvyJdHm6oa76acnFXjwvqUU5q1G3w8PEUx3/uITewHY9Mx2ercUWEmf89DLheyTbZiUewy3jTQwFz8xrkRMFrQixkZ0sz5xDPTsRM7/Jc1MBJy9aaN8n9kNiEdbFd3mls5pVroFmUtUfTjNTq9UFcZ8hoU+Fl/QDKHvLkdnn78KFJI53j+v7Vxe1+BwERZT+AvPxjWyBhyBQ2DtIVvzpCHpZ68tCwXi38OCw/aPUCXWInmseMq78naPJXDcrDm4GNYFE7nFA+962723X0ajGEbbAhEfsuRdtkyPKTeoIzqG14PAWBa/7srh5C64v0hxOg+wYsZ9xW45Xzfck5pzhLY+C117zOQuicTo8gNhhSXw73K7T3ex2BHwA6Ju8GXdwFA1dyzlgRRQTdbOJmRh/MPrKRNg/BQ6f4fGPzuNZC7zfrTstlme74XfEuF6VYrwzTVOHVvAZFt4N1k7ddpRkoYYlc8ZW6iUkPB2RyLwQ4e5VHmiDzMVMq2djIoY/XQK11xyuXaC8GYvZw516wrsmY9ZCQ7QDLuadHo0dXdeoYC7mYrUvLiSiQP17jPqqpt/IzWHWIVkx0HmpdicccsdaAJrqpUiRlKwdYsGIRGIN0t2WjHhaADQPx46VSFtmZUfT1srNu5TjSehSJ1NF2r7PeW5QzJPPAL8empIDUKSuta2T6CShakIYjGuCLcboDMuONFaTVG9eoeU8kKruveC63UWzJAcKFoxINnV9uxBlOHOFNRV5NR4HCL8e6UaYqIU4IFIj8MZz2GMkP16pLyZeiiYdyevUYHFT X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: f042a092-cfac-4945-4080-08da8403d8e7 X-MS-Exchange-CrossTenant-AuthSource: AM7PR04MB7046.eurprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 22 Aug 2022 06:02:08.7816 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: b5K8J3SNOn+S7Om8r7s+WGZ/7epQN00OWr3EwiuNxF+ih75yzYUvtnkTh7VESypFfXfec7rGqM45W6gsT1eudA== X-MS-Exchange-Transport-CrossTenantHeadersStamped: VI1PR04MB5135 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220821_230213_421275_1DEB6712 X-CRM114-Status: GOOD ( 20.75 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Freescale i.MX8qxp pixel link MSI bus is a simple memory-mapped bus. It is used to access peripherals in i.MX8qm/qxp imaging, LVDS, MIPI DSI and HDMI TX subsystems, like I2C controller, PWM controller, MIPI DSI controller and Control and Status Registers (CSR) module. Reference simple-pm-bus bindings and add Freescale i.MX8qxp pixel link MSI bus specific bindings. Signed-off-by: Liu Ying Reviewed-by: Rob Herring --- v3->v4: * Add child nodes in the example MSI bus node of the MSI bus dt-binding. (Krzysztof) * Resend v4 to imply this patch is based on v6.0-rc1 so that there are not any dependencies. (Rob) v2->v3: * Add a pattern property to allow child nodes. (Rob) v1->v2: Address Krzysztof's comments: * Add a select to explicitly select the MSI bus dt-binding. * List 'simple-pm-bus' explicitly as one item of compatible strings. * Require compatible and reg properties. * Put reg property just after compatible property in example. .../bus/fsl,imx8qxp-pixel-link-msi-bus.yaml | 232 ++++++++++++++++++ 1 file changed, 232 insertions(+) create mode 100644 Documentation/devicetree/bindings/bus/fsl,imx8qxp-pixel-link-msi-bus.yaml diff --git a/Documentation/devicetree/bindings/bus/fsl,imx8qxp-pixel-link-msi-bus.yaml b/Documentation/devicetree/bindings/bus/fsl,imx8qxp-pixel-link-msi-bus.yaml new file mode 100644 index 000000000000..b568d0ce438d --- /dev/null +++ b/Documentation/devicetree/bindings/bus/fsl,imx8qxp-pixel-link-msi-bus.yaml @@ -0,0 +1,232 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/bus/fsl,imx8qxp-pixel-link-msi-bus.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Freescale i.MX8qxp Pixel Link Medium Speed Interconnect (MSI) Bus + +maintainers: + - Liu Ying + +description: | + i.MX8qxp pixel link MSI bus is used to control settings of PHYs, I/Os + sitting together with the PHYs. It is not the same as the MSI bus coming + from i.MX8 System Controller Unit (SCU) which is used to control power, + clock and reset through the i.MX8 Distributed Slave System Controller (DSC). + + i.MX8qxp pixel link MSI bus is a simple memory-mapped bus. Two input clocks, + that is, MSI clock and AHB clock, need to be enabled so that peripherals + connected to the bus can be accessed. Also, the bus is part of a power + domain. The power domain needs to be enabled before the peripherals can + be accessed. + + Peripherals in i.MX8qm/qxp imaging, LVDS, MIPI DSI and HDMI TX subsystems, + like I2C controller, PWM controller, MIPI DSI controller and Control and + Status Registers (CSR) module, are accessed through the bus. + + The i.MX System Controller Firmware (SCFW) owns and uses the i.MX8qm/qxp + pixel link MSI bus controller and does not allow SCFW user to control it. + So, the controller's registers cannot be accessed by SCFW user. Hence, + the interrupts generated by the controller don't make any sense from SCFW + user's point of view. + +allOf: + - $ref: simple-pm-bus.yaml# + +# We need a select here so we don't match all nodes with 'simple-pm-bus'. +select: + properties: + compatible: + contains: + enum: + - fsl,imx8qxp-display-pixel-link-msi-bus + - fsl,imx8qm-display-pixel-link-msi-bus + required: + - compatible + +properties: + compatible: + items: + - enum: + - fsl,imx8qxp-display-pixel-link-msi-bus + - fsl,imx8qm-display-pixel-link-msi-bus + - const: simple-pm-bus + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + items: + - description: master gated clock from system + - description: AHB clock + + clock-names: + items: + - const: msi + - const: ahb + +patternProperties: + "^.*@[0-9a-f]+$": + description: Devices attached to the bus + type: object + properties: + reg: + maxItems: 1 + + required: + - reg + +required: + - compatible + - reg + - clocks + - clock-names + - power-domains + +unevaluatedProperties: false + +examples: + - | + #include + #include + bus@56200000 { + compatible = "fsl,imx8qxp-display-pixel-link-msi-bus", "simple-pm-bus"; + reg = <0x56200000 0x20000>; + #address-cells = <1>; + #size-cells = <1>; + interrupt-parent = <&dc0_irqsteer>; + interrupts = <320>; + ranges; + clocks = <&dc0_disp_ctrl_link_mst0_lpcg IMX_LPCG_CLK_4>, + <&dc0_disp_ctrl_link_mst0_lpcg IMX_LPCG_CLK_4>; + clock-names = "msi", "ahb"; + power-domains = <&pd IMX_SC_R_DC_0>; + + syscon@56221000 { + compatible = "fsl,imx8qxp-mipi-lvds-csr", "syscon", "simple-mfd"; + reg = <0x56221000 0x1000>; + clocks = <&mipi_lvds_0_di_mipi_lvds_regs_lpcg IMX_LPCG_CLK_4>; + clock-names = "ipg"; + + pxl2dpi { + compatible = "fsl,imx8qxp-pxl2dpi"; + fsl,sc-resource = ; + power-domains = <&pd IMX_SC_R_MIPI_0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + + mipi_lvds_0_pxl2dpi_dc0_pixel_link0: endpoint@0 { + reg = <0>; + remote-endpoint = <&dc0_pixel_link0_mipi_lvds_0_pxl2dpi>; + }; + + mipi_lvds_0_pxl2dpi_dc0_pixel_link1: endpoint@1 { + reg = <1>; + remote-endpoint = <&dc0_pixel_link1_mipi_lvds_0_pxl2dpi>; + }; + }; + + port@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + + mipi_lvds_0_pxl2dpi_mipi_lvds_0_ldb_ch0: endpoint@0 { + reg = <0>; + remote-endpoint = <&mipi_lvds_0_ldb_ch0_mipi_lvds_0_pxl2dpi>; + }; + + mipi_lvds_0_pxl2dpi_mipi_lvds_0_ldb_ch1: endpoint@1 { + reg = <1>; + remote-endpoint = <&mipi_lvds_0_ldb_ch1_mipi_lvds_0_pxl2dpi>; + }; + }; + }; + }; + + ldb { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx8qxp-ldb"; + clocks = <&clk IMX_SC_R_LVDS_0 IMX_SC_PM_CLK_MISC2>, + <&clk IMX_SC_R_LVDS_0 IMX_SC_PM_CLK_BYPASS>; + clock-names = "pixel", "bypass"; + power-domains = <&pd IMX_SC_R_LVDS_0>; + + channel@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + phys = <&mipi_lvds_0_phy>; + phy-names = "lvds_phy"; + + port@0 { + reg = <0>; + + mipi_lvds_0_ldb_ch0_mipi_lvds_0_pxl2dpi: endpoint { + remote-endpoint = <&mipi_lvds_0_pxl2dpi_mipi_lvds_0_ldb_ch0>; + }; + }; + + port@1 { + reg = <1>; + + /* ... */ + }; + }; + + channel@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + phys = <&mipi_lvds_0_phy>; + phy-names = "lvds_phy"; + + port@0 { + reg = <0>; + + mipi_lvds_0_ldb_ch1_mipi_lvds_0_pxl2dpi: endpoint { + remote-endpoint = <&mipi_lvds_0_pxl2dpi_mipi_lvds_0_ldb_ch1>; + }; + }; + + port@1 { + reg = <1>; + + /* ... */ + }; + }; + }; + }; + + clock-controller@56223004 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x56223004 0x4>; + #clock-cells = <1>; + clocks = <&mipi_lvds_0_ipg_clk>; + clock-indices = ; + clock-output-names = "mipi_lvds_0_di_mipi_lvds_regs_lpcg_ipg_clk"; + power-domains = <&pd IMX_SC_R_MIPI_0>; + }; + + phy@56228300 { + compatible = "fsl,imx8qxp-mipi-dphy"; + reg = <0x56228300 0x100>; + clocks = <&clk IMX_SC_R_LVDS_0 IMX_SC_PM_CLK_PHY>; + clock-names = "phy_ref"; + #phy-cells = <0>; + fsl,syscon = <&mipi_lvds_0_csr>; + power-domains = <&pd IMX_SC_R_MIPI_0>; + }; + };