From patchwork Mon Aug 22 19:14:18 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Serge Semin X-Patchwork-Id: 12951299 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id D743DC28D13 for ; Mon, 22 Aug 2022 19:39:42 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:CC:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=9pCTI7iDHjmSEoWXmUKiHPml6ppwrLZZwyz0RthEZpo=; b=FxR6+NhBXKqptf DMkRYMeAJZi6lvThgmWCaIQhcUdKwtqIb9G6yTTE2plzkboHm41AzkQWmLAyttMs/e14i9RQGWxFA X9MifP1kXYIQHe+mnoW3GfwcpAs7Fe1QhQ49BwLvchNHjV5AZIawyXTW9DJaF5T5Gf/GZXxEZZCXp kjpEwMLTK+kjpODpzSLE2J+ufEDFtLfDEeUDQ5Zq79vK+MUP6JEL2uWCR8G5eE1Wyd7+hHVgIQma4 2XB7bU9sZnInm6wwB5jSpnDSzAqG4obRSs20SFYV9vp2nPgMKChTYnUJoxQ1TN4qlawQUd1ZmlsF0 GJL7ngaMNpIZ42jhzTIg==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1oQDFR-00E865-Se; Mon, 22 Aug 2022 19:38:10 +0000 Received: from mail.baikalelectronics.com ([87.245.175.230]) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1oQCsq-00Dvkx-Pu for linux-arm-kernel@lists.infradead.org; Mon, 22 Aug 2022 19:14:52 +0000 Received: from mail (mail.baikal.int [192.168.51.25]) by mail.baikalelectronics.com (Postfix) with ESMTP id 4EACBDAC; Mon, 22 Aug 2022 22:17:49 +0300 (MSK) DKIM-Filter: OpenDKIM Filter v2.11.0 mail.baikalelectronics.com 4EACBDAC DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baikalelectronics.ru; s=mail; t=1661195869; bh=K258ftqJ/6fH7i95l7cXsjWtgIhNBwGLWowAwjCwKj0=; h=From:To:CC:Subject:Date:In-Reply-To:References:From; b=A6Y21ZpjdjAxP9Lbd3+1n7Cniqk7fJj7TxX1HZqeSTZYdi+lw0l15xzpifuwwt0zJ zzBsag98A8meYSYD8/9T+y3K/GOQp0vQY1Lj36S+eBWIR9mbxfpzSEyMjuNJXWg0Ac CEdl+KTpNggkq8VOb2bgLo8gQb+dsBjMCly6nxQk= Received: from localhost (192.168.168.10) by mail (192.168.51.25) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Mon, 22 Aug 2022 22:14:35 +0300 From: Serge Semin To: Michal Simek , Borislav Petkov , Mauro Carvalho Chehab , Tony Luck , James Morse , Robert Richter CC: Serge Semin , Serge Semin , Alexey Malahov , Michail Ivanov , Pavel Parkhomenko , Punnaiah Choudary Kalluri , Manish Narani , Dinh Nguyen , , , Subject: [PATCH 09/18] EDAC/synopsys: Set actual DIMM ECC errors grain Date: Mon, 22 Aug 2022 22:14:18 +0300 Message-ID: <20220822191427.27969-10-Sergey.Semin@baikalelectronics.ru> In-Reply-To: <20220822191427.27969-1-Sergey.Semin@baikalelectronics.ru> References: <20220822191427.27969-1-Sergey.Semin@baikalelectronics.ru> MIME-Version: 1.0 X-ClientProxiedBy: MAIL.baikal.int (192.168.51.25) To mail (192.168.51.25) X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220822_121449_145168_6E47DAAE X-CRM114-Status: GOOD ( 14.58 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org It was wrong to set the DIMM errors grain parameter to just 1 byte because DW uMCTL2 DDRC calculates ECC for each SDRAM word and passes it as an additional byte of data to the memory chips. SDRAM word is the actual DQ-bus width determined by the DQ-width set during the IP-core synthesize and the DQ-bus mode (part of the DQ-bus actually used to get data from the memory chips) selected during the DDR controller initial setup procedure. Thus let's set the MCI DIMMs grain based on these parameters determined during the DW uMCTL2 DDRC config getting procedure. Signed-off-by: Serge Semin --- drivers/edac/synopsys_edac.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/drivers/edac/synopsys_edac.c b/drivers/edac/synopsys_edac.c index e7f8d448850b..af34a83dc1ef 100644 --- a/drivers/edac/synopsys_edac.c +++ b/drivers/edac/synopsys_edac.c @@ -26,9 +26,6 @@ /* Number of channels per memory controller */ #define SNPS_EDAC_NR_CHANS 1 -/* Granularity of reported error in bytes */ -#define SNPS_EDAC_ERR_GRAIN 1 - #define SNPS_EDAC_MSG_SIZE 256 #define SNPS_EDAC_MOD_STRING "snps_edac" @@ -733,9 +730,12 @@ static void snps_init_csrows(struct mem_ctl_info *mci) struct snps_edac_priv *priv = mci->pvt_info; struct csrow_info *csi; struct dimm_info *dimm; - u32 size, row; + u32 size, row, width; int j; + /* Actual SDRAM-word width for which ECC is calculated */ + width = 1U << (priv->info.dq_width - priv->info.dq_mode); + for (row = 0; row < mci->nr_csrows; row++) { csi = mci->csrows[row]; size = snps_get_memsize(); @@ -745,7 +745,7 @@ static void snps_init_csrows(struct mem_ctl_info *mci) dimm->edac_mode = EDAC_SECDED; dimm->mtype = priv->info.sdram_mode; dimm->nr_pages = (size >> PAGE_SHIFT) / csi->nr_channels; - dimm->grain = SNPS_EDAC_ERR_GRAIN; + dimm->grain = width; dimm->dtype = priv->info.dev_cfg; } }