From patchwork Mon Aug 22 19:19:51 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Serge Semin X-Patchwork-Id: 12951345 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 23565C28D13 for ; Mon, 22 Aug 2022 20:02:01 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:CC:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=z85Z/6OdJQC1+VZnL/Y7rdPK5wVYxvPQeAOQf1JxLHQ=; b=bg3rCcbvh55KJy dfWnn024NE1xuGWydQSs7OER1j/APoaIc+8jzjK4pHSqh3GPnJbfL4arjZbY7i9TQ4ImfvFHu84H4 bX5frSnIutDU+7LEOcH1R35J5CqlSMLkL70YBy9+8y2z6AZfiLIcudR2ZvhLMMB2TG84SL0u+ynSA hhMVo37tZwdGaU+gy7X+GwZn41nm02V0MmtROftoVSnNrDmdMYkAOE2z0TZsiHyTkYiR4qaOozK7w c1WOFMerMyqeWaNjUQpMCtu+XJK/ZwN1x81XGpxWxx/68PgkLMxKmXxJqjZrae/dTREOyGSJwBNCX VZ2SBGqalXYXSAnX9eIg==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1oQDb3-00EK0L-C6; Mon, 22 Aug 2022 20:00:29 +0000 Received: from mail.baikalelectronics.com ([87.245.175.230]) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1oQCyM-00Dyp9-Ix for linux-arm-kernel@lists.infradead.org; Mon, 22 Aug 2022 19:20:36 +0000 Received: from mail (mail.baikal.int [192.168.51.25]) by mail.baikalelectronics.com (Postfix) with ESMTP id 3BA08DAA; Mon, 22 Aug 2022 22:23:35 +0300 (MSK) DKIM-Filter: OpenDKIM Filter v2.11.0 mail.baikalelectronics.com 3BA08DAA DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baikalelectronics.ru; s=mail; t=1661196215; bh=7ylqOa6KtJzxYsNaCkDs3IPpzbBntgjWaRfez9/K1Vg=; h=From:To:CC:Subject:Date:In-Reply-To:References:From; b=ZPsh344g5kt09WPZsyhHNO38n/ilN/AlbJxS/8zp9Wau0lzTuZlXkvFCCFGcLjiJe cL2hGjmz8g3fT3NqvM8NhOvfvYkfbdmqdCjrott2er7/ZbwODJkaPQgcf+hQrlYN1b Xg61HbCBp94tu2Vxccvz3kBA4jT4DkD+di8rb1OM= Received: from localhost (192.168.168.10) by mail (192.168.51.25) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Mon, 22 Aug 2022 22:20:21 +0300 From: Serge Semin To: Michal Simek , Borislav Petkov , Mauro Carvalho Chehab , Tony Luck , James Morse , Robert Richter CC: Serge Semin , Serge Semin , Alexey Malahov , Michail Ivanov , Pavel Parkhomenko , Punnaiah Choudary Kalluri , Manish Narani , Dinh Nguyen , Rob Herring , Krzysztof Kozlowski , , , , Subject: [PATCH 08/13] EDAC/synopsys: Add individual named ECC IRQs support Date: Mon, 22 Aug 2022 22:19:51 +0300 Message-ID: <20220822191957.28546-9-Sergey.Semin@baikalelectronics.ru> In-Reply-To: <20220822191957.28546-1-Sergey.Semin@baikalelectronics.ru> References: <20220822191957.28546-1-Sergey.Semin@baikalelectronics.ru> MIME-Version: 1.0 X-ClientProxiedBy: MAIL.baikal.int (192.168.51.25) To mail (192.168.51.25) X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220822_122031_131854_E372C047 X-CRM114-Status: GOOD ( 21.09 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Currently the DW uMCTL2 DDRC EDAC driver supports a common unnamed IRQ only. It isn't suitable for our platform which has the individual IRQ lines for each DDRC event (ECC UE, ECC CE, DFI parity error, Scrubber done, etc). Moreover the DW uMCTL2 DDRC IP-core doesn't have an option to be configured with a common interrupts output line. So in order to have the generic DW uMCTL2 DDR controller and our platform supported by the driver we need to add the individual, per DDRC event, IRQs request support. There is not much to do really since the common IRQs handler has already been split up into the sub-handlers. So the only thing we need to do is first try to request the individual IRQs, if failed then fallback to the common IRQ. The IRQ names are used in accordance with the DW uMCTL2 DDRC DT-bindings. Signed-off-by: Serge Semin --- drivers/edac/synopsys_edac.c | 91 ++++++++++++++++++++++++++++++++---- 1 file changed, 81 insertions(+), 10 deletions(-) diff --git a/drivers/edac/synopsys_edac.c b/drivers/edac/synopsys_edac.c index ac0123ff4595..e7d59238c5ca 100644 --- a/drivers/edac/synopsys_edac.c +++ b/drivers/edac/synopsys_edac.c @@ -1524,25 +1524,96 @@ static void snps_mc_free(struct mem_ctl_info *mci) edac_mc_free(mci); } -static int snps_setup_irq(struct mem_ctl_info *mci) +/** + * snps_request_ind_irq - Request individual DDRC IRQs. + * @mci: EDAC memory controller instance. + * + * Return: 0 if the IRQs were successfully requested, 1 if the individual IRQs + * are unavailable, otherwise negative errno. + */ +static int snps_request_ind_irq(struct mem_ctl_info *mci) { struct snps_edac_priv *priv = mci->pvt_info; - int ret, irq; + struct device *dev = &priv->pdev->dev; + int rc, irq; - irq = platform_get_irq(priv->pdev, 0); - if (irq < 0) { - edac_printk(KERN_ERR, EDAC_MC, - "No IRQ %d in DT\n", irq); + irq = platform_get_irq_byname_optional(priv->pdev, "ecc_ce"); + if (irq == -ENXIO) + return 1; + if (irq < 0) + return irq; + + rc = devm_request_irq(dev, irq, snps_ce_irq_handler, 0, "ecc_ce", mci); + if (rc) { + edac_printk(KERN_ERR, EDAC_MC, "Failed to request ECC CE IRQ\n"); + return rc; + } + + irq = platform_get_irq_byname(priv->pdev, "ecc_ue"); + if (irq < 0) return irq; + + rc = devm_request_irq(dev, irq, snps_ue_irq_handler, 0, "ecc_ue", mci); + if (rc) { + edac_printk(KERN_ERR, EDAC_MC, "Failed to request ECC UE IRQ\n"); + return rc; + } + + return 0; +} + +/** + * snps_request_com_irq - Request common DDRC IRQ. + * @mci: EDAC memory controller instance. + * + * It first attempts to get the named IRQ. If failed the method fallbacks + * to first available one. + * + * Return: 0 if the IRQ was successfully requested otherwise negative errno. + */ +static int snps_request_com_irq(struct mem_ctl_info *mci) +{ + struct snps_edac_priv *priv = mci->pvt_info; + struct device *dev = &priv->pdev->dev; + int rc, irq; + + irq = platform_get_irq_byname_optional(priv->pdev, "ecc"); + if (irq < 0) { + irq = platform_get_irq(priv->pdev, 0); + if (irq < 0) + return irq; } - ret = devm_request_irq(&priv->pdev->dev, irq, snps_com_irq_handler, - 0, dev_name(&priv->pdev->dev), mci); - if (ret < 0) { + rc = devm_request_irq(dev, irq, snps_com_irq_handler, 0, "ecc", mci); + if (rc) { edac_printk(KERN_ERR, EDAC_MC, "Failed to request IRQ\n"); - return ret; + return rc; } + return 0; +} + +/** + * snps_setup_irq - Request and enable DDRC IRQs. + * @mci: EDAC memory controller instance. + * + * It first tries to get and request individual IRQs. If failed the method + * fallbacks to the common IRQ line case. The IRQs will be enabled only if + * some of these requests have been successful. + * + * Return: 0 if IRQs were successfully setup otherwise negative errno. + */ +static int snps_setup_irq(struct mem_ctl_info *mci) +{ + struct snps_edac_priv *priv = mci->pvt_info; + int rc; + + rc = snps_request_ind_irq(mci); + if (rc > 0) + rc = snps_request_com_irq(mci); + if (rc) + return rc; + snps_enable_irq(priv); return 0;