From patchwork Tue Aug 23 09:09:59 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mike Leach X-Patchwork-Id: 12951892 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id C1779C32772 for ; Tue, 23 Aug 2022 09:11:58 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:MIME-Version:List-Subscribe:List-Help: List-Post:List-Archive:List-Unsubscribe:List-Id:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=u9+uTx+hSEFrEfe47gNu2lVDuCoqMPeaZGmu/5uReXg=; b=qT2YonCYsNvzjJ lE3g4iMFQ1OCn73xBCjUAG6EySogEeM/FTbjs1pexD++F3YT5TbvRjag+dYm+ER0G2O1K5nr7gxMY pi9HgGuNMuOh89j26Ex1XPCdQFF3FoG6nUWNNXoFGxmWnvKSNQthaHbKb/0MiRzQZ6BQUHakVgP23 eE9JTXnko2NJ6q+JiFPezuOi/mm7oM3czwKUH8xY80+AtXSgnrtQMOdZ8rTV6xLv2y6wo+7r967yK Q4BlNHLoj+hsmZ88zkq7fCzfgC2v0t/85jkh/MCqlw082FjnrARj250gIg/7baZQvNUz0dYb4P9rj RXsVNsSblVrSDqgXonrA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1oQPvv-004KZY-E2; Tue, 23 Aug 2022 09:10:51 +0000 Received: from mail-wm1-x330.google.com ([2a00:1450:4864:20::330]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1oQPvO-004KLW-CI for linux-arm-kernel@lists.infradead.org; Tue, 23 Aug 2022 09:10:21 +0000 Received: by mail-wm1-x330.google.com with SMTP id ay39-20020a05600c1e2700b003a5503a80cfso7365470wmb.2 for ; Tue, 23 Aug 2022 02:10:17 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=references:in-reply-to:message-id:date:subject:cc:to:from:from:to :cc; bh=pwmExfB0GU/JJ9bsvT+Z4EqrCVu9SNKAksEtRHBxI8c=; b=JrVszevmPoPRbfiTb8pNhNUMQ8h8MlWsdluTSJDr5PNDrh75e47+DkY8auefPEavd2 s9msH0uwJ6ykCDBW6Ky9QIWXtl2Gne4XxfHXxiL1OAsPz+2ATtS43XYO+qeQXly1IXiY 8LchZl/DvRDYTaAQkhI8kYm+JGNC9vTxaibR74ntM7a7IjaEgj3b+Zn5Dk3qSIfBTR/B nJDl89MomryEn0BrkLrlconJXlkq2J3kBgB/YaiSzm92HK3AcFYkshwt9tJNHMGvKE6v zukMAahTvSis5JeKxQINGyd77UWAXw9Uezpg8FmeTwv2HyE3XRBzq4CfUUHIKBIOZ32B siew== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=references:in-reply-to:message-id:date:subject:cc:to:from :x-gm-message-state:from:to:cc; bh=pwmExfB0GU/JJ9bsvT+Z4EqrCVu9SNKAksEtRHBxI8c=; b=pPDWmI2vRib9CzVkCOEvo3iQN6Sw2ftCi6FllwvvTXE3htczwcnoVbYd751O9LtD/9 9FfaSGR1wLch/ACkkXwODLWIWD10GYowHgWy+N2a6FXHKZ8GFg5b6+2IOousUqB7q0Ex y2EHrq3DgYBF7Cvc3q7jetROWwWBqPS8I4q7ftuNPZlHIBAAyokNZecctv2Ib0NPnHOF efj+p4Ncn+MVgSxOEp1LPDFvywX305jBZmI+8RMNo/RTef2+fL1/buBgNUnTFu0gWjmY be7D2LJB+sz/jZSiSu8VUafbHL+JDhCDfcbVygWSP5974FXIVigc+31i1ytnUawGRjlo irlQ== X-Gm-Message-State: ACgBeo2iRQfN63YBIsOYYcHRebf3muHAfXjsDxU5xXGFSDTo5GFIm/6J Ysx/pPFNe6D8e1pFPeJGbvDRTQ== X-Google-Smtp-Source: AA6agR4rg6Y6twComjcMtlk5VkVPbVh3CjSnqC3K84LjaoswTCOevLdnZmNZgO2Buv+dzMChUqDRdg== X-Received: by 2002:a05:600c:1d16:b0:3a6:1fa1:41f7 with SMTP id l22-20020a05600c1d1600b003a61fa141f7mr1456118wms.103.1661245816834; Tue, 23 Aug 2022 02:10:16 -0700 (PDT) Received: from linaro.org ([2a00:23c5:6809:2201:4553:cf11:6cff:b293]) by smtp.gmail.com with ESMTPSA id w6-20020adfde86000000b002253d162491sm10760721wrl.52.2022.08.23.02.10.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 23 Aug 2022 02:10:16 -0700 (PDT) From: Mike Leach To: coresight@lists.linaro.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Cc: mathieu.poirier@linaro.org, suzuki.poulose@arm.com, peterz@infradead.org, mingo@redhat.com, acme@kernel.org, linux-perf-users@vger.kernel.org, leo.yan@linaro.org, quic_jinlmao@quicinc.com, Mike Leach Subject: [PATCH v4 03/13] coresight: stm: Update STM driver to use Trace ID API Date: Tue, 23 Aug 2022 10:09:59 +0100 Message-Id: <20220823091009.14121-4-mike.leach@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20220823091009.14121-1-mike.leach@linaro.org> References: <20220823091009.14121-1-mike.leach@linaro.org> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220823_021018_467041_57B45B1A X-CRM114-Status: GOOD ( 19.87 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Updates the STM driver to use the trace ID allocation API. This uses the _system_id calls to allocate an ID on device poll, and release on device remove. The sysfs access to the STMTRACEIDR register has been changed from RW to RO. Having this value as writable is not appropriate for the new Trace ID scheme - and had potential to cause errors in the previous scheme if values clashed with other sources. Signed-off-by: Mike Leach Reviewed-by: Suzuki K Poulose --- drivers/hwtracing/coresight/coresight-stm.c | 41 +++++++-------------- 1 file changed, 14 insertions(+), 27 deletions(-) diff --git a/drivers/hwtracing/coresight/coresight-stm.c b/drivers/hwtracing/coresight/coresight-stm.c index bb14a3a8a921..9ef3e923a930 100644 --- a/drivers/hwtracing/coresight/coresight-stm.c +++ b/drivers/hwtracing/coresight/coresight-stm.c @@ -31,6 +31,7 @@ #include #include "coresight-priv.h" +#include "coresight-trace-id.h" #define STMDMASTARTR 0xc04 #define STMDMASTOPR 0xc08 @@ -615,24 +616,7 @@ static ssize_t traceid_show(struct device *dev, val = drvdata->traceid; return sprintf(buf, "%#lx\n", val); } - -static ssize_t traceid_store(struct device *dev, - struct device_attribute *attr, - const char *buf, size_t size) -{ - int ret; - unsigned long val; - struct stm_drvdata *drvdata = dev_get_drvdata(dev->parent); - - ret = kstrtoul(buf, 16, &val); - if (ret) - return ret; - - /* traceid field is 7bit wide on STM32 */ - drvdata->traceid = val & 0x7f; - return size; -} -static DEVICE_ATTR_RW(traceid); +static DEVICE_ATTR_RO(traceid); #define coresight_stm_reg(name, offset) \ coresight_simple_reg32(struct stm_drvdata, name, offset) @@ -819,14 +803,6 @@ static void stm_init_default_data(struct stm_drvdata *drvdata) */ drvdata->stmsper = ~0x0; - /* - * The trace ID value for *ETM* tracers start at CPU_ID * 2 + 0x10 and - * anything equal to or higher than 0x70 is reserved. Since 0x00 is - * also reserved the STM trace ID needs to be higher than 0x00 and - * lowner than 0x10. - */ - drvdata->traceid = 0x1; - /* Set invariant transaction timing on all channels */ bitmap_clear(drvdata->chs.guaranteed, 0, drvdata->numsp); } @@ -854,7 +830,7 @@ static void stm_init_generic_data(struct stm_drvdata *drvdata, static int stm_probe(struct amba_device *adev, const struct amba_id *id) { - int ret; + int ret, trace_id; void __iomem *base; struct device *dev = &adev->dev; struct coresight_platform_data *pdata = NULL; @@ -938,12 +914,22 @@ static int stm_probe(struct amba_device *adev, const struct amba_id *id) goto stm_unregister; } + trace_id = coresight_trace_id_get_system_id(); + if (trace_id < 0) { + ret = trace_id; + goto cs_unregister; + } + drvdata->traceid = (u8)trace_id; + pm_runtime_put(&adev->dev); dev_info(&drvdata->csdev->dev, "%s initialized\n", (char *)coresight_get_uci_data(id)); return 0; +cs_unregister: + coresight_unregister(drvdata->csdev); + stm_unregister: stm_unregister_device(&drvdata->stm); return ret; @@ -953,6 +939,7 @@ static void stm_remove(struct amba_device *adev) { struct stm_drvdata *drvdata = dev_get_drvdata(&adev->dev); + coresight_trace_id_put_system_id(drvdata->traceid); coresight_unregister(drvdata->csdev); stm_unregister_device(&drvdata->stm);