diff mbox series

[v1,6/8] arm64: dts: verdin-imx8mp: add pcie support

Message ID 20220922162925.2368577-7-marcel@ziswiler.com (mailing list archive)
State New, archived
Headers show
Series arm64: dts: verdin-imx8mm: verdin-imx8mp: pcie. et. al. | expand

Commit Message

Marcel Ziswiler Sept. 22, 2022, 4:29 p.m. UTC 
From: Marcel Ziswiler <marcel.ziswiler@toradex.com>

Add PCIe support on the Verdin iMX8M Plus.

Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>

---
This still relies on the PHY part landing [1] and the internal SYSPLL
mode getting sorted [2].

[1] https://lore.kernel.org/all/1663659498-5180-1-git-send-email-hongxing.zhu@nxp.com/
[2] https://lore.kernel.org/all/AS8PR04MB867657D03C61774096A5A1628C4C9@AS8PR04MB8676.eurprd04.prod.outlook.com/

 .../dts/freescale/imx8mp-verdin-dahlia.dtsi   |  9 +++++++-
 .../boot/dts/freescale/imx8mp-verdin.dtsi     | 22 ++++++++++++++++++-
 2 files changed, 29 insertions(+), 2 deletions(-)

Comments

Shawn Guo Oct. 23, 2022, 1:12 p.m. UTC | #1 
On Thu, Sep 22, 2022 at 06:29:23PM +0200, Marcel Ziswiler wrote:
> From: Marcel Ziswiler <marcel.ziswiler@toradex.com>
> 
> Add PCIe support on the Verdin iMX8M Plus.
> 
> Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
> 
> ---
> This still relies on the PHY part landing [1] and the internal SYSPLL
> mode getting sorted [2].
> 
> [1] https://lore.kernel.org/all/1663659498-5180-1-git-send-email-hongxing.zhu@nxp.com/
> [2] https://lore.kernel.org/all/AS8PR04MB867657D03C61774096A5A1628C4C9@AS8PR04MB8676.eurprd04.prod.outlook.com/

Are these dependencies already landed on v6.1-rc1?

Shawn

> 
>  .../dts/freescale/imx8mp-verdin-dahlia.dtsi   |  9 +++++++-
>  .../boot/dts/freescale/imx8mp-verdin.dtsi     | 22 ++++++++++++++++++-
>  2 files changed, 29 insertions(+), 2 deletions(-)
> 
> diff --git a/arch/arm64/boot/dts/freescale/imx8mp-verdin-dahlia.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-verdin-dahlia.dtsi
> index 4b8f86f63081..60f9dc4847db 100644
> --- a/arch/arm64/boot/dts/freescale/imx8mp-verdin-dahlia.dtsi
> +++ b/arch/arm64/boot/dts/freescale/imx8mp-verdin-dahlia.dtsi
> @@ -67,7 +67,14 @@ &i2c4 {
>  	/* TODO: Audio Codec */
>  };
>  
> -/* TODO: Verdin PCIE_1 */
> +/* Verdin PCIE_1 */
> +&pcie {
> +	status = "okay";
> +};
> +
> +&pcie_phy {
> +	status = "okay";
> +};
>  
>  /* Verdin PWM_1 */
>  &pwm1 {
> diff --git a/arch/arm64/boot/dts/freescale/imx8mp-verdin.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-verdin.dtsi
> index 7be7e922927b..160bb32cb5f7 100644
> --- a/arch/arm64/boot/dts/freescale/imx8mp-verdin.dtsi
> +++ b/arch/arm64/boot/dts/freescale/imx8mp-verdin.dtsi
> @@ -734,7 +734,27 @@ eeprom_carrier_board: eeprom@57 {
>  	};
>  };
>  
> -/* TODO: Verdin PCIE_1 */
> +/* Verdin PCIE_1 */
> +&pcie {
> +	assigned-clocks = <&clk IMX8MP_CLK_PCIE_AUX>;
> +	assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_50M>;
> +	assigned-clock-rates = <10000000>;
> +	clocks = <&clk IMX8MP_CLK_HSIO_ROOT>,
> +		 <&clk IMX8MP_CLK_PCIE_ROOT>,
> +		 <&clk IMX8MP_CLK_HSIO_AXI>;
> +	clock-names = "pcie", "pcie_aux", "pcie_bus";
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&pinctrl_pcie>;
> +	/* PCIE_1_RESET# (SODIMM 244) */
> +	reset-gpio = <&gpio4 19 GPIO_ACTIVE_LOW>;
> +};
> +
> +&pcie_phy {
> +	clocks = <&clk IMX8MP_CLK_HSIO_ROOT>;
> +	clock-names = "ref";
> +	fsl,clkreq-unsupported;
> +	fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_OUTPUT>;
> +};
>  
>  /* Verdin PWM_1 */
>  &pwm1 {
> -- 
> 2.36.1
>
Marcel Ziswiler Oct. 23, 2022, 9:46 p.m. UTC | #2 
Hi Shawn

On Sun, 2022-10-23 at 21:12 +0800, Shawn Guo wrote:
> On Thu, Sep 22, 2022 at 06:29:23PM +0200, Marcel Ziswiler wrote:
> > From: Marcel Ziswiler <marcel.ziswiler@toradex.com>
> > 
> > Add PCIe support on the Verdin iMX8M Plus.
> > 
> > Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
> > 
> > ---
> > This still relies on the PHY part landing [1] and the internal SYSPLL
> > mode getting sorted [2].
> > 
> > [1] https://lore.kernel.org/all/1663659498-5180-1-git-send-email-hongxing.zhu@nxp.com/
> > [2]
> > https://lore.kernel.org/all/AS8PR04MB867657D03C61774096A5A1628C4C9@AS8PR04MB8676.eurprd04.prod.outlook.com/
> 
> Are these dependencies already landed on v6.1-rc1?

No, but [1] Vinod pulled into -next on October 17 so we should be fine. Actually, your pull of [3] into -next
as of September 17 is more important, as otherwise that pcie and pcie_phy node I'm referencing would not exist
yet. Of course, it will only be really functional once [2] also gets sorted. However, it should really not hurt
already having it in there.

Thanks!

[3] https://lore.kernel.org/all/1662109086-15881-1-git-send-email-hongxing.zhu@nxp.com/

> Shawn
> 
> > ly 
> >  .../dts/freescale/imx8mp-verdin-dahlia.dtsi   |  9 +++++++-
> >  .../boot/dts/freescale/imx8mp-verdin.dtsi     | 22 ++++++++++++++++++-
> >  2 files changed, 29 insertions(+), 2 deletions(-)
> > 
> > diff --git a/arch/arm64/boot/dts/freescale/imx8mp-verdin-dahlia.dtsi
> > b/arch/arm64/boot/dts/freescale/imx8mp-verdin-dahlia.dtsi
> > index 4b8f86f63081..60f9dc4847db 100644
> > --- a/arch/arm64/boot/dts/freescale/imx8mp-verdin-dahlia.dtsi
> > +++ b/arch/arm64/boot/dts/freescale/imx8mp-verdin-dahlia.dtsi
> > @@ -67,7 +67,14 @@ &i2c4 {
> >         /* TODO: Audio Codec */
> >  };
> >  
> > -/* TODO: Verdin PCIE_1 */
> > +/* Verdin PCIE_1 */
> > +&pcie {
> > +       status = "okay";
> > +};
> > +
> > +&pcie_phy {
> > +       status = "okay";
> > +};
> >  
> >  /* Verdin PWM_1 */
> >  &pwm1 {
> > diff --git a/arch/arm64/boot/dts/freescale/imx8mp-verdin.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-
> > verdin.dtsi
> > index 7be7e922927b..160bb32cb5f7 100644
> > --- a/arch/arm64/boot/dts/freescale/imx8mp-verdin.dtsi
> > +++ b/arch/arm64/boot/dts/freescale/imx8mp-verdin.dtsi
> > @@ -734,7 +734,27 @@ eeprom_carrier_board: eeprom@57 {
> >         };
> >  };
> >  
> > -/* TODO: Verdin PCIE_1 */
> > +/* Verdin PCIE_1 */
> > +&pcie {
> > +       assigned-clocks = <&clk IMX8MP_CLK_PCIE_AUX>;
> > +       assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_50M>;
> > +       assigned-clock-rates = <10000000>;
> > +       clocks = <&clk IMX8MP_CLK_HSIO_ROOT>,
> > +                <&clk IMX8MP_CLK_PCIE_ROOT>,
> > +                <&clk IMX8MP_CLK_HSIO_AXI>;
> > +       clock-names = "pcie", "pcie_aux", "pcie_bus";
> > +       pinctrl-names = "default";
> > +       pinctrl-0 = <&pinctrl_pcie>;
> > +       /* PCIE_1_RESET# (SODIMM 244) */
> > +       reset-gpio = <&gpio4 19 GPIO_ACTIVE_LOW>;
> > +};
> > +
> > +&pcie_phy {
> > +       clocks = <&clk IMX8MP_CLK_HSIO_ROOT>;
> > +       clock-names = "ref";
> > +       fsl,clkreq-unsupported;
> > +       fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_OUTPUT>;
> > +};
> >  
> >  /* Verdin PWM_1 */
> >  &pwm1 {
> > -- 
> > 2.36.1

Cheers

Marcel
diff mbox series

Patch

diff --git a/arch/arm64/boot/dts/freescale/imx8mp-verdin-dahlia.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-verdin-dahlia.dtsi
index 4b8f86f63081..60f9dc4847db 100644
--- a/arch/arm64/boot/dts/freescale/imx8mp-verdin-dahlia.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mp-verdin-dahlia.dtsi
@@ -67,7 +67,14 @@  &i2c4 {
 	/* TODO: Audio Codec */
 };
 
-/* TODO: Verdin PCIE_1 */
+/* Verdin PCIE_1 */
+&pcie {
+	status = "okay";
+};
+
+&pcie_phy {
+	status = "okay";
+};
 
 /* Verdin PWM_1 */
 &pwm1 {
diff --git a/arch/arm64/boot/dts/freescale/imx8mp-verdin.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-verdin.dtsi
index 7be7e922927b..160bb32cb5f7 100644
--- a/arch/arm64/boot/dts/freescale/imx8mp-verdin.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mp-verdin.dtsi
@@ -734,7 +734,27 @@  eeprom_carrier_board: eeprom@57 {
 	};
 };
 
-/* TODO: Verdin PCIE_1 */
+/* Verdin PCIE_1 */
+&pcie {
+	assigned-clocks = <&clk IMX8MP_CLK_PCIE_AUX>;
+	assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_50M>;
+	assigned-clock-rates = <10000000>;
+	clocks = <&clk IMX8MP_CLK_HSIO_ROOT>,
+		 <&clk IMX8MP_CLK_PCIE_ROOT>,
+		 <&clk IMX8MP_CLK_HSIO_AXI>;
+	clock-names = "pcie", "pcie_aux", "pcie_bus";
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_pcie>;
+	/* PCIE_1_RESET# (SODIMM 244) */
+	reset-gpio = <&gpio4 19 GPIO_ACTIVE_LOW>;
+};
+
+&pcie_phy {
+	clocks = <&clk IMX8MP_CLK_HSIO_ROOT>;
+	clock-names = "ref";
+	fsl,clkreq-unsupported;
+	fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_OUTPUT>;
+};
 
 /* Verdin PWM_1 */
 &pwm1 {