diff mbox series

clocksource/drivers/arm_arch_timer: Fix CNTPCT_LO and CNTVCT_LO value

Message ID 20220926113003.13121-1-zhangshaokun@hisilicon.com (mailing list archive)
State New, archived
Headers show
Series clocksource/drivers/arm_arch_timer: Fix CNTPCT_LO and CNTVCT_LO value | expand

Commit Message

Shaokun Zhang Sept. 26, 2022, 11:30 a.m. UTC 
From: Yang Guo <guoyang2@huawei.com>

CNTPCT_LO and CNTVCT_LO are defined by mistake in commit '8b82c4f883a7',
so fix them according to the Arm ARM as follows:

Offset    Register      Type Description
0x000     CNTPCT[31:0]  RO   Physical Count register.
0x004     CNTPCT[63:32] RO
0x008     CNTVCT[31:0]  RO   Virtual Count register.
0x00C     CNTVCT[63:32] RO

Fixes: 8b82c4f883a7 ("clocksource/drivers/arm_arch_timer: Move MMIO timer programming over to CVAL")
Cc: Marc Zyngier <maz@kernel.org>
Cc: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Yang Guo <guoyang2@huawei.com>
Signed-off-by: Shaokun Zhang <zhangshaokun@hisilicon.com>
---
 drivers/clocksource/arm_arch_timer.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

Comments

Marc Zyngier Sept. 26, 2022, 12:46 p.m. UTC | #1 
On Mon, 26 Sep 2022 07:30:03 -0400,
Shaokun Zhang <zhangshaokun@hisilicon.com> wrote:

Please Cc the clocksource maintainers (now added) so that they know
what is going on.

> 
> From: Yang Guo <guoyang2@huawei.com>
> 
> CNTPCT_LO and CNTVCT_LO are defined by mistake in commit '8b82c4f883a7',
> so fix them according to the Arm ARM as follows:

Please quote the location of the information: DDi 0487I.a, Table I2-4
"CNTBaseN memory map"

> 
> Offset    Register      Type Description
> 0x000     CNTPCT[31:0]  RO   Physical Count register.
> 0x004     CNTPCT[63:32] RO
> 0x008     CNTVCT[31:0]  RO   Virtual Count register.
> 0x00C     CNTVCT[63:32] RO
> 
> Fixes: 8b82c4f883a7 ("clocksource/drivers/arm_arch_timer: Move MMIO timer programming over to CVAL")

Cc: stable@vger.kernel.org

> Cc: Marc Zyngier <maz@kernel.org>
> Cc: Mark Rutland <mark.rutland@arm.com>
> Signed-off-by: Yang Guo <guoyang2@huawei.com>
> Signed-off-by: Shaokun Zhang <zhangshaokun@hisilicon.com>

With the above:

Acked-by: Marc Zyngier <maz@kernel.org>

	M.
Shaokun Zhang Sept. 26, 2022, 1:12 p.m. UTC | #2 
Hi Marc,

在 2022/9/26 20:46, Marc Zyngier 写道:
> On Mon, 26 Sep 2022 07:30:03 -0400,
> Shaokun Zhang <zhangshaokun@hisilicon.com> wrote:
> 
> Please Cc the clocksource maintainers (now added) so that they know
> what is going on.
> 

Oops，I only Cced Mark and you and will add the two in V2.

>>
>> From: Yang Guo <guoyang2@huawei.com>
>>
>> CNTPCT_LO and CNTVCT_LO are defined by mistake in commit '8b82c4f883a7',
>> so fix them according to the Arm ARM as follows:
> 
> Please quote the location of the information: DDi 0487I.a, Table I2-4
> "CNTBaseN memory map"
> 

Sure.

>>
>> Offset    Register      Type Description
>> 0x000     CNTPCT[31:0]  RO   Physical Count register.
>> 0x004     CNTPCT[63:32] RO
>> 0x008     CNTVCT[31:0]  RO   Virtual Count register.
>> 0x00C     CNTVCT[63:32] RO
>>
>> Fixes: 8b82c4f883a7 ("clocksource/drivers/arm_arch_timer: Move MMIO timer programming over to CVAL")
> 
> Cc: stable@vger.kernel.org
> 

It's was introduced in Linux 5.16, Shall I Cc stable?

>> Cc: Marc Zyngier <maz@kernel.org>
>> Cc: Mark Rutland <mark.rutland@arm.com>
>> Signed-off-by: Yang Guo <guoyang2@huawei.com>
>> Signed-off-by: Shaokun Zhang <zhangshaokun@hisilicon.com>
> 
> With the above:
> 
> Acked-by: Marc Zyngier <maz@kernel.org>
> 

Thanks Marc,
Shaokun

> 	M.
>
Marc Zyngier Sept. 26, 2022, 1:17 p.m. UTC | #3 
On Mon, 26 Sep 2022 09:12:15 -0400,
Shaokun Zhang <zhangshaokun@hisilicon.com> wrote:
> 
> Hi Marc,
> 
> 在 2022/9/26 20:46, Marc Zyngier 写道:
> > On Mon, 26 Sep 2022 07:30:03 -0400,
> > Shaokun Zhang <zhangshaokun@hisilicon.com> wrote:
> > 
> > Please Cc the clocksource maintainers (now added) so that they know
> > what is going on.
> > 
> 
> Oops，I only Cced Mark and you and will add the two in V2.
> 
> >>
> >> From: Yang Guo <guoyang2@huawei.com>
> >>
> >> CNTPCT_LO and CNTVCT_LO are defined by mistake in commit '8b82c4f883a7',
> >> so fix them according to the Arm ARM as follows:
> > 
> > Please quote the location of the information: DDi 0487I.a, Table I2-4
> > "CNTBaseN memory map"
> > 
> 
> Sure.
> 
> >>
> >> Offset    Register      Type Description
> >> 0x000     CNTPCT[31:0]  RO   Physical Count register.
> >> 0x004     CNTPCT[63:32] RO
> >> 0x008     CNTVCT[31:0]  RO   Virtual Count register.
> >> 0x00C     CNTVCT[63:32] RO
> >>
> >> Fixes: 8b82c4f883a7 ("clocksource/drivers/arm_arch_timer: Move MMIO timer programming over to CVAL")
> > 
> > Cc: stable@vger.kernel.org
> > 
> 
> It's was introduced in Linux 5.16, Shall I Cc stable?

Yes, as this will need to be backported to 5.19 at the very least.

Thanks,

	M.
diff mbox series

Patch

diff --git a/drivers/clocksource/arm_arch_timer.c b/drivers/clocksource/arm_arch_timer.c
index 9ab8221ee3c6..8122a1646925 100644
--- a/drivers/clocksource/arm_arch_timer.c
+++ b/drivers/clocksource/arm_arch_timer.c
@@ -44,8 +44,8 @@ 
 #define CNTACR_RWVT	BIT(4)
 #define CNTACR_RWPT	BIT(5)
 
-#define CNTVCT_LO	0x00
-#define CNTPCT_LO	0x08
+#define CNTPCT_LO	0x00
+#define CNTVCT_LO	0x08
 #define CNTFRQ		0x10
 #define CNTP_CVAL_LO	0x20
 #define CNTP_CTL	0x2c