From patchwork Tue Sep 27 14:19:21 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Marek_Beh=C3=BAn?= X-Patchwork-Id: 12990702 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id EC6D4C6FA82 for ; Tue, 27 Sep 2022 14:22:04 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=7m4eBqhAh08ce+LtdjFGTcKzyh850WLmWyxYnUeuAck=; b=F6CII1rZD8M88y AbHvQQmpqxSp5QBFZefShx1LxqftajTFMX4sz2yb3hpWYUUN3bAxNCZa5bq+UOdmdrDXgHhwkLJ5M Fq97YgoB/loxaDMvcYwuB53RS1S4zNmAbqnQLx9j/7ZvChgKjJT6exTUI0e2th678h3b7RP/fRzDs GoMMScMOf6Lbf5QISuejn2pR1fFPs85KMyX2d8GUknyiDwanOvtxReEV2NTQT9TQG62ET/nkE2a/g O+iYSc4V1lrPPR47x7UM0n64N8zA/wBBbdQMNoxS+BxPpY1TolmnuyZiGuun8sUnHX0QEkKjTk8kS uECSacYNyyPUHladjOqQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1odBSD-00BBVg-J6; Tue, 27 Sep 2022 14:20:57 +0000 Received: from ams.source.kernel.org ([145.40.68.75]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1odBR2-00BB3j-6J for linux-arm-kernel@lists.infradead.org; Tue, 27 Sep 2022 14:19:45 +0000 Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ams.source.kernel.org (Postfix) with ESMTPS id A4E9FB81C17; Tue, 27 Sep 2022 14:19:42 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 9CD86C43470; Tue, 27 Sep 2022 14:19:39 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1664288381; bh=YOHpPreByGGoyZO9gaJvQCWGWwT25levFv1BixvDFn4=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=C2garZzaK4Pg6GrBqg5oZs3ujiWgC77GzEjxlYtYv4KH5CNh+h9NYIgN8kn41yeTY qmRAHheaUVC4fMIMMVY9QjuD5bDDlfEvrqKZZTYaHfD4R9ANGiViR2KnT5YNII8zvU iQcLt/jOr788Ym8oCHtOG4dlhgIgocKg5Icknv0Ou1cuC31UpY3uOSBbYCxUuQpgz9 jlolo890KePtLoF0cMLRBnkUioT8dhzStuMQm75+ZeZrPK7SnXTfP7DWGbh890Zz5f t4VuJ+JtyVgoq4sGccG7wN0VaPx2CBt/ghDGJThinNb57oRHukNOu3cCv7I3Chhnt0 WTAa8MNqq3VFQ== From: =?utf-8?q?Marek_Beh=C3=BAn?= To: Lorenzo Pieralisi Cc: Bjorn Helgaas , Gregory CLEMENT , pali@kernel.org, =?utf-8?q?K?= =?utf-8?q?rzysztof_Wilczy=C5=84ski?= , linux-pci@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Miquel Raynal , =?utf-8?q?Marek_Beh=C3=BAn?= Subject: [PATCH v2 05/10] PCI: aardvark: Add clock support Date: Tue, 27 Sep 2022 16:19:21 +0200 Message-Id: <20220927141926.8895-6-kabel@kernel.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220927141926.8895-1-kabel@kernel.org> References: <20220927141926.8895-1-kabel@kernel.org> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220927_071944_538758_9A132F33 X-CRM114-Status: GOOD ( 17.86 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org From: Miquel Raynal The IP relies on a gated clock. When we will add S2RAM support, this clock will need to be resumed before any PCIe registers are accessed. Add support for this clock. Signed-off-by: Miquel Raynal Signed-off-by: Pali Rohár Signed-off-by: Marek Behún --- drivers/pci/controller/pci-aardvark.c | 32 +++++++++++++++++++++++++++ 1 file changed, 32 insertions(+) diff --git a/drivers/pci/controller/pci-aardvark.c b/drivers/pci/controller/pci-aardvark.c index 03e318bc171f..3beafc893969 100644 --- a/drivers/pci/controller/pci-aardvark.c +++ b/drivers/pci/controller/pci-aardvark.c @@ -9,6 +9,7 @@ */ #include +#include #include #include #include @@ -297,6 +298,7 @@ struct advk_pcie { struct timer_list link_irq_timer; struct pci_bridge_emul bridge; struct gpio_desc *reset_gpio; + struct clk *clk; struct phy *phy; }; @@ -1809,6 +1811,29 @@ static int advk_pcie_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) return of_irq_parse_and_map_pci(dev, slot, pin); } +static int advk_pcie_setup_clk(struct advk_pcie *pcie) +{ + struct device *dev = &pcie->pdev->dev; + int ret; + + pcie->clk = devm_clk_get(dev, NULL); + if (IS_ERR(pcie->clk) && (PTR_ERR(pcie->clk) == -EPROBE_DEFER)) + return PTR_ERR(pcie->clk); + + /* Old bindings miss the clock handle */ + if (IS_ERR(pcie->clk)) { + dev_warn(dev, "Clock unavailable (%ld)\n", PTR_ERR(pcie->clk)); + pcie->clk = NULL; + return 0; + } + + ret = clk_prepare_enable(pcie->clk); + if (ret) + dev_err(dev, "Clock initialization failed (%d)\n", ret); + + return ret; +} + static void advk_pcie_disable_phy(struct advk_pcie *pcie) { phy_power_off(pcie->phy); @@ -2000,6 +2025,10 @@ static int advk_pcie_probe(struct platform_device *pdev) slot_power_limit / 1000, (slot_power_limit / 100) % 10); + ret = advk_pcie_setup_clk(pcie); + if (ret) + return ret; + ret = advk_pcie_setup_phy(pcie); if (ret) return ret; @@ -2122,6 +2151,9 @@ static int advk_pcie_remove(struct platform_device *pdev) /* Disable phy */ advk_pcie_disable_phy(pcie); + /* Disable clock */ + clk_disable_unprepare(pcie->clk); + return 0; }