From patchwork Thu Sep 29 12:03:41 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Machon X-Patchwork-Id: 12993977 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 3CA64C433FE for ; Thu, 29 Sep 2022 11:58:53 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:CC:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=sOTLhMZvkkV15dKOxQAjJKzf6tT9kkutQT+zOKEvl1s=; b=KjfiCz9e/xD2JP F3Dx+qJtXqDyPzZOIcBaAkExoXzfDRZohmaXY3RwSfe0YBt6KQWmREpep3mRN5OF616w6IslrEsFH 3Q0mrTjn45B9uPI86F+Sr/e+3VShqt9po24GiTaRV4/raaaHz5ZCN6szct3YBnMI/2SbFMVW2ZMFi ZqeUCSjDaWUuVx3x9ueftMBK/wpJSFQSUsF7fb29v/IlV2aNaBCo2cwAOaW/dERz6pEQfYZ3mNjUT Yf/dVM/QeJXdslYra4D281HwlZ5HWx4zQV04xOwqkAfpyOEx6Xy9NuIxxE6Zcghm8m5mSWHEyB5At 7xSj0E2vAYzNESQ4JmlQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1odsAp-002nYS-4F; Thu, 29 Sep 2022 11:57:51 +0000 Received: from esa.microchip.iphmx.com ([68.232.154.123]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1ods87-002mEI-8P for linux-arm-kernel@lists.infradead.org; Thu, 29 Sep 2022 11:55:06 +0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1664452503; x=1695988503; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=3KKi/OR9C962XpjIXhKDs4nNa0pgZ6XGruR8ipalK4g=; b=IVkwaO1MvF+PoKbulvLTVYtxnMavvcWFn2zogIUiGNCg46YJAfFgDJbH JkC7emFK4phZJp6+8NDECGE+hLcO4vad14tJY7Wou/sgqnBLMUNrAHSmv wYtZLocChhrZ7oXvC1PWj/tuA4sz/kRdKy1XyIhu76E0qij2sO6l+WMV8 mzRxQ4nVGONZi3O19+fjMNy+tucL42baSIgREBbo2JP1502smtKWwofQE fMN2pWmb0hPKWdCpuZCFv2a/s0NmBJyuoj3mO2sDiIpE/NtrnRTpRsDHx e+RKv46LhrQIIhs2kpF6VRHh+y6HeUJAfg6N54yngLDd10fFv95XmNtLD A==; X-IronPort-AV: E=Sophos;i="5.93,355,1654585200"; d="scan'208";a="179507756" Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa2.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 29 Sep 2022 04:54:49 -0700 Received: from chn-vm-ex03.mchp-main.com (10.10.85.151) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.12; Thu, 29 Sep 2022 04:54:37 -0700 Received: from DEN-LT-70577.microchip.com (10.10.115.15) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server id 15.1.2507.12 via Frontend Transport; Thu, 29 Sep 2022 04:54:34 -0700 From: Daniel Machon To: CC: , , , , , , , , , , , , , , , , , Subject: [PATCH net-next 5/6] net: microchip: sparx5: add support for offloading dscp table Date: Thu, 29 Sep 2022 14:03:41 +0200 Message-ID: <20220929120342.2069359-6-daniel.machon@microchip.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220929120342.2069359-1-daniel.machon@microchip.com> References: <20220929120342.2069359-1-daniel.machon@microchip.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220929_045503_432198_0C01C83D X-CRM114-Status: GOOD ( 20.77 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Add support for offloading dscp app entries. Dscp values are global for all ports on the sparx5 switch. Therefore, we replicate each dscp app entry per-port. Signed-off-by: Daniel Machon --- .../ethernet/microchip/sparx5/sparx5_dcb.c | 62 ++++++++++++++++++- .../ethernet/microchip/sparx5/sparx5_port.c | 39 ++++++++++++ .../ethernet/microchip/sparx5/sparx5_port.h | 9 +++ 3 files changed, 108 insertions(+), 2 deletions(-) diff --git a/drivers/net/ethernet/microchip/sparx5/sparx5_dcb.c b/drivers/net/ethernet/microchip/sparx5/sparx5_dcb.c index 10aeb422b1ae..0cc46672b59c 100644 --- a/drivers/net/ethernet/microchip/sparx5/sparx5_dcb.c +++ b/drivers/net/ethernet/microchip/sparx5/sparx5_dcb.c @@ -34,6 +34,13 @@ static int sparx5_dcb_app_validate(struct net_device *dev, int err = 0; switch (app->selector) { + /* Dscp checks */ + case IEEE_8021QAZ_APP_SEL_DSCP: + if (app->protocol > 63) + err = -EINVAL; + else if (app->priority >= SPX5_PRIOS) + err = -ERANGE; + break; /* Pcp checks */ case DCB_APP_SEL_PCP: if (app->protocol > 15) @@ -104,12 +111,20 @@ static int sparx5_dcb_app_update(struct net_device *dev) struct dcb_app app_itr = { .selector = DCB_APP_SEL_PCP }; struct sparx5_port *port = netdev_priv(dev); struct sparx5_port_qos_pcp_map *pcp_map; + struct dcb_ieee_app_dscp_map *dscp_map; struct sparx5_port_qos qos = {0}; int portno = port->portno; int i; + dscp_map = &qos.dscp.map; pcp_map = &qos.pcp.map; + /* Get dscp ingress mapping */ + dcb_ieee_getapp_dscp_prio_mask_map(dev, dscp_map); + for (i = 0; i < ARRAY_SIZE(dscp_map->map); i++) + if (dscp_map->map[i]) + dscp_map->map[i] = fls(dscp_map->map[i]) - 1; + /* Get pcp ingress mapping */ for (i = 0; i < ARRAY_SIZE(pcp_map->map); i++) { app_itr.protocol = i; @@ -122,9 +137,44 @@ static int sparx5_dcb_app_update(struct net_device *dev) qos.pcp.dp_enable = qos.pcp.qos_enable; } + /* Enable use of dscp for queue classification ? */ + if (sparx5_dcb_apptrust_contains(portno, IEEE_8021QAZ_APP_SEL_DSCP)) { + qos.dscp.qos_enable = true; + qos.dscp.dp_enable = qos.dscp.qos_enable; + } + return sparx5_port_qos_set(port, &qos); } +/* Set or delete dscp app entry. + * + * Dscp mapping is global for all ports, so set and delete app entries are + * replicated for each port. + */ +static int sparx5_dcb_ieee_dscp_setdel_app(struct net_device *dev, + struct dcb_app *app, bool del) +{ + struct sparx5_port *port = netdev_priv(dev); + struct dcb_app apps[SPX5_PORTS]; + struct sparx5_port *port_itr; + int err, i; + + for (i = 0; i < SPX5_PORTS; i++) { + port_itr = port->sparx5->ports[i]; + if (!port_itr) + continue; + memcpy(&apps[i], app, sizeof(struct dcb_app)); + if (del) + err = dcb_ieee_delapp(port_itr->ndev, &apps[i]); + else + err = dcb_ieee_setapp(port_itr->ndev, &apps[i]); + if (err) + return err; + } + + return 0; +} + static int sparx5_dcb_ieee_setapp(struct net_device *dev, struct dcb_app *app) { struct dcb_app app_itr; @@ -143,7 +193,11 @@ static int sparx5_dcb_ieee_setapp(struct net_device *dev, struct dcb_app *app) dcb_ieee_delapp(dev, &app_itr); } - err = dcb_ieee_setapp(dev, app); + if (app->selector == IEEE_8021QAZ_APP_SEL_DSCP) + err = sparx5_dcb_ieee_dscp_setdel_app(dev, app, false); + else + err = dcb_ieee_setapp(dev, app); + if (err) goto out; @@ -157,7 +211,11 @@ static int sparx5_dcb_ieee_delapp(struct net_device *dev, struct dcb_app *app) { int err; - err = dcb_ieee_delapp(dev, app); + if (app->selector == IEEE_8021QAZ_APP_SEL_DSCP) + err = sparx5_dcb_ieee_dscp_setdel_app(dev, app, true); + else + err = dcb_ieee_delapp(dev, app); + if (err < 0) return err; diff --git a/drivers/net/ethernet/microchip/sparx5/sparx5_port.c b/drivers/net/ethernet/microchip/sparx5/sparx5_port.c index 99e86e87aa16..fb5e321c4896 100644 --- a/drivers/net/ethernet/microchip/sparx5/sparx5_port.c +++ b/drivers/net/ethernet/microchip/sparx5/sparx5_port.c @@ -1149,6 +1149,7 @@ void sparx5_port_enable(struct sparx5_port *port, bool enable) int sparx5_port_qos_set(struct sparx5_port *port, struct sparx5_port_qos *qos) { + sparx5_port_qos_dscp_set(port, &qos->dscp); sparx5_port_qos_pcp_set(port, &qos->pcp); return 0; @@ -1181,3 +1182,41 @@ int sparx5_port_qos_pcp_set(const struct sparx5_port *port, return 0; } + +int sparx5_port_qos_dscp_set(const struct sparx5_port *port, + struct sparx5_port_qos_dscp *qos) +{ + struct sparx5 *sparx5 = port->sparx5; + u8 *dscp = qos->map.map; + int i; + + /* Enable/disable dscp and dp for qos classification. + * Disable rewrite of dscp values for now. + */ + spx5_rmw(ANA_CL_QOS_CFG_DSCP_QOS_ENA_SET(qos->qos_enable) | + ANA_CL_QOS_CFG_DSCP_DP_ENA_SET(qos->dp_enable) | + ANA_CL_QOS_CFG_DSCP_KEEP_ENA_SET(1), + ANA_CL_QOS_CFG_DSCP_QOS_ENA | ANA_CL_QOS_CFG_DSCP_DP_ENA | + ANA_CL_QOS_CFG_DSCP_KEEP_ENA, sparx5, + ANA_CL_QOS_CFG(port->portno)); + + /* Map each dscp value to priority and dp */ + for (i = 0; i < ARRAY_SIZE(qos->map.map); i++) { + spx5_rmw(ANA_CL_DSCP_CFG_DSCP_QOS_VAL_SET(*(dscp + i)) | + ANA_CL_DSCP_CFG_DSCP_DP_VAL_SET(0), + ANA_CL_DSCP_CFG_DSCP_QOS_VAL | + ANA_CL_DSCP_CFG_DSCP_DP_VAL, sparx5, + ANA_CL_DSCP_CFG(i)); + } + + /* Set per-dscp trust */ + for (i = 0; i < ARRAY_SIZE(qos->map.map); i++) { + if (qos->qos_enable) { + spx5_rmw(ANA_CL_DSCP_CFG_DSCP_TRUST_ENA_SET(1), + ANA_CL_DSCP_CFG_DSCP_TRUST_ENA, sparx5, + ANA_CL_DSCP_CFG(i)); + } + } + + return 0; +} diff --git a/drivers/net/ethernet/microchip/sparx5/sparx5_port.h b/drivers/net/ethernet/microchip/sparx5/sparx5_port.h index fae9f5464548..00def02455a7 100644 --- a/drivers/net/ethernet/microchip/sparx5/sparx5_port.h +++ b/drivers/net/ethernet/microchip/sparx5/sparx5_port.h @@ -101,8 +101,15 @@ struct sparx5_port_qos_pcp { bool dp_enable; }; +struct sparx5_port_qos_dscp { + struct dcb_ieee_app_dscp_map map; + bool qos_enable; + bool dp_enable; +}; + struct sparx5_port_qos { struct sparx5_port_qos_pcp pcp; + struct sparx5_port_qos_dscp dscp; }; int sparx5_port_qos_set(struct sparx5_port *port, struct sparx5_port_qos *qos); @@ -110,4 +117,6 @@ int sparx5_port_qos_set(struct sparx5_port *port, struct sparx5_port_qos *qos); int sparx5_port_qos_pcp_set(const struct sparx5_port *port, struct sparx5_port_qos_pcp *qos); +int sparx5_port_qos_dscp_set(const struct sparx5_port *port, + struct sparx5_port_qos_dscp *qos); #endif /* __SPARX5_PORT_H__ */