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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: 1OTYOpWhKO/imG51HahsBpkd6ipBRwx3NLdsVmCBxRsMWsaM7YS5Yx4HT2KXFSn9zPr2YykeT3u+nb+3vV0tRhIOaQ7cAfIA8vA9jNClthKJ+MZbrnRBNVLYZYs67q/ONVC7lZoOI7H5nX4xo9AmGc7fxhm3ExeS6WWjxfHzu+8bgPFsi46KiKTtFDqgxfVcHntHwfvl0qedVel0DPK6R9xrLrShrXpbb+ntmilSQlNSt4PoN4d9M/RT3SyLCKtFHE9YRuoPvAmQp8QFtipbq7kuRmzuh5QeLZWzA6+c/T1crPtrk+zMB9FE3sNMvJmKWl+jLS88q/kbODJDMmc8zspTni4SdBhGwYDZsnnIxsvjdn/Z/UwokVHJRsCCpMPjfvm5eyfWu7P9ZbrVCGsGw5BwO4RRWY7rj/fYks7jJR4UGZZ87upDcH9j8hQEj9DcaApWmWPVTbczDKWeXP8EzzLBHcxdPnWg3sBzCwmPgNIk09myZk8DXbh3Xh3GwpKyUnPSM1+D/8kBs54VcQ1xAnSGqYmDtL+UF81cNMeiqzNMBBk3CfqZrUUOj6nr2jmmDVA34/vB9o3B4F8S/cURH6C7N15YsDW4LVz+LfDPogviP4OYjgdtKsKpjlCsRbtydwzJR7UJc9y1NdSJnG8TMw5Jfly67n0Kt7vdCLvnaqVTtS679bU8t+tkVFJAbU88qYPusH2swtBR7YAcWAvjhYbYK8t9KvWJKPlJbg6mOO7S6NEEDleP1GYwVPQtRqZDnswubOheh+MvtkVi3VtfINIcGdUKiuDmd5+hNjLPQrViEscgMpma2B8TbatAqILa+MDN84SMLMKaUkhuBpGB3Z/T00fe8YlbZO7uLSlrvUVPowcAGtInvpXNIBuAekLO3nkSumK78vAjHYxkS6ZCIAXVB0ZKe6bd9PmcbwTL6i4BECJ5tADIFoHOvG4oBgzGqjNasOPYvF/OfbBAHD7uXUa9cr52gXNV7Y7FwUqVspnK+4sDhVZ9VKq8bFetkXbnOoCc+DA1DaXJju3U9rwS/orLhsrhEHRq5XH5Nw7ABc+h4fJ8bm1ZttX7vAshTPCkP0Q5skqoeIskw+XHb3O9Wm6oltuq+QobffgVPONCQW71zEByYWHApyJRPv8kQikagNxHCJZSXN6U2rkzmXugwlQQoB1fsgsYCYOc68EAZ+CMam2/+LpbtJltT5JiECJ1J/EyoHqKblGs7U7JTMueKkhpRT0Ao/gz8a56sucHt9z7IKakuNxyYH291GrEt1Xnmvd1m2abKfi4U7s5k+ZHNcxFkXgX7QNj8ZutB5a7c6bHzUNb9njTaf04m/iIdEp8Ht4FJg5r9poZkNTUFWR9iCbsQgRn5bQ+1hJBWu5Wyz0tN2/Wa2Frtbf+yQZ9wam0mNWgLJIxMDM3MfaCQ2ZZjsI1PGydg7LnArFidXl/YhKKV1OZP6spaiURc/+G8LY2LnHEVDOr/OhSZ4e8et5ha4Uvt8LV2snx8F3PhtMGt2DtQm4SZqcoE6udvzee/YNKe7W1F1TjYkqFVHLSze00bsWb+LiMfp1weOAKSidWXjGJaMiUNYxk4OSUwQtwbEUcc3vBHmLn5ykd3joulZ1mTA== X-OriginatorOrg: plvision.eu X-MS-Exchange-CrossTenant-Network-Message-Id: 8134490f-2db2-41dc-ea03-08daa78bb870 X-MS-Exchange-CrossTenant-AuthSource: VI1P190MB0317.EURP190.PROD.OUTLOOK.COM X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 06 Oct 2022 11:12:56.4296 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 03707b74-30f3-46b6-a0e0-ff0a7438c9c4 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: Jh7YoaXP76bw7wfMVM9EV6euF+dQNKPruug7QJ6EkVVYr06ySjUXDyEO2CRT83UWB2yOaGmszoAkIaTC9DvkwfM1UbS/MdN9XTuXZa9/PAI= X-MS-Exchange-Transport-CrossTenantHeadersStamped: DU0P190MB1929 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20221006_041305_492883_14AF696A X-CRM114-Status: GOOD ( 15.05 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org From: Yuval Shaia AC5 requieres different handling for MSI as with armada8k. Fix it by: 1. Enabling the relevant bits in init phase 2. Dispatch virtual IRQ handlers when MSI interrupts are received Also enable/disable PCIE_APP_LTSSM for AC5. Signed-off-by: Yuval Shaia Signed-off-by: Vadym Kochan --- drivers/pci/controller/dwc/pcie-armada8k.c | 28 ++++++++++++++++++++-- 1 file changed, 26 insertions(+), 2 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-armada8k.c b/drivers/pci/controller/dwc/pcie-armada8k.c index b025d23bb058..c2a285e33e90 100644 --- a/drivers/pci/controller/dwc/pcie-armada8k.c +++ b/drivers/pci/controller/dwc/pcie-armada8k.c @@ -45,6 +45,7 @@ struct armada8k_pcie { #define PCIE_GLOBAL_CONTROL_REG (PCIE_VENDOR_REGS_OFFSET + 0x0) #define PCIE_APP_LTSSM_EN BIT(2) +#define PCIE_APP_LTSSM_EN_AC5 BIT(24) #define PCIE_DEVICE_TYPE_SHIFT 4 #define PCIE_DEVICE_TYPE_MASK 0xF #define PCIE_DEVICE_TYPE_RC 0x4 /* Root complex */ @@ -64,6 +65,7 @@ struct armada8k_pcie { #define PCIE_INT_B_ASSERT_MASK_AC5 BIT(13) #define PCIE_INT_C_ASSERT_MASK_AC5 BIT(14) #define PCIE_INT_D_ASSERT_MASK_AC5 BIT(15) +#define PCIE_MSI_MASK_AC5 BIT(11) #define PCIE_ARCACHE_TRC_REG (PCIE_VENDOR_REGS_OFFSET + 0x50) #define PCIE_AWCACHE_TRC_REG (PCIE_VENDOR_REGS_OFFSET + 0x54) @@ -167,16 +169,30 @@ static int armada8k_pcie_link_up(struct dw_pcie *pci) static int armada8k_pcie_start_link(struct dw_pcie *pci) { + struct armada8k_pcie *pcie = to_armada8k_pcie(pci); u32 reg; /* Start LTSSM */ reg = dw_pcie_readl_dbi(pci, PCIE_GLOBAL_CONTROL_REG); - reg |= PCIE_APP_LTSSM_EN; + if (pcie->pcie_type == MVPCIE_TYPE_AC5) + reg |= PCIE_APP_LTSSM_EN_AC5; + else + reg |= PCIE_APP_LTSSM_EN; dw_pcie_writel_dbi(pci, PCIE_GLOBAL_CONTROL_REG, reg); return 0; } +void ac5_pcie_msi_init(struct dw_pcie *pci) +{ + u32 val; + + /* Set MSI bit in interrupt mask */ + val = dw_pcie_readl_dbi(pci, PCIE_GLOBAL_INT_MASK1_REG); + val |= PCIE_MSI_MASK_AC5; + dw_pcie_writel_dbi(pci, PCIE_GLOBAL_INT_MASK1_REG, val); +} + static int armada8k_pcie_host_init(struct dw_pcie_rp *pp) { u32 reg; @@ -186,7 +202,10 @@ static int armada8k_pcie_host_init(struct dw_pcie_rp *pp) if (!dw_pcie_link_up(pci)) { /* Disable LTSSM state machine to enable configuration */ reg = dw_pcie_readl_dbi(pci, PCIE_GLOBAL_CONTROL_REG); - reg &= ~(PCIE_APP_LTSSM_EN); + if (pcie->pcie_type == MVPCIE_TYPE_AC5) + reg &= ~(PCIE_APP_LTSSM_EN_AC5); + else + reg &= ~(PCIE_APP_LTSSM_EN); dw_pcie_writel_dbi(pci, PCIE_GLOBAL_CONTROL_REG, reg); } @@ -226,6 +245,9 @@ static int armada8k_pcie_host_init(struct dw_pcie_rp *pp) dw_pcie_writel_dbi(pci, PCIE_GLOBAL_INT_MASK1_REG, reg); } + if (IS_ENABLED(CONFIG_PCI_MSI) && (pcie->pcie_type == MVPCIE_TYPE_AC5)) + ac5_pcie_msi_init(pci); + return 0; } @@ -242,6 +264,8 @@ static irqreturn_t armada8k_pcie_irq_handler(int irq, void *arg) */ val = dw_pcie_readl_dbi(pci, PCIE_GLOBAL_INT_CAUSE1_REG); dw_pcie_writel_dbi(pci, PCIE_GLOBAL_INT_CAUSE1_REG, val); + if ((PCIE_MSI_MASK_AC5 & val) && (pcie->pcie_type == MVPCIE_TYPE_AC5)) + dw_handle_msi_irq(&pci->pp); return IRQ_HANDLED; }